CP3SP33SMSSLASHNOPB datasheet(68/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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13 Interrupts

The Interrupt Control Unit (ICU) receives interrupt requests from internal and external sources and

generates interrupts to the CPU. The highest-priority interrupt is the NonMaskable Interrupt (NMI), which is

triggered by a falling edge received on the NMI input pin.

The maskable interrupts (IRQn) have a fixed, linear priority from IRQ0 through IRQ70, in which IRQ0 has

the lowest priority and IRQ70 has the highest priority. IRQ0 is not implemented, so IRQ1 is the lowest

priority maskable interrupt that may occur in normal operation.

13.1 Non-Maskable Interrupts

The Interrupt Control Unit (ICU) receives the external NMI input and generates the NMI signal driven to

the CPU. The NMI input is an asynchronous input with Schmitt trigger characteristics and an internal

synchronization circuit, therefore no external synchronizing circuit is needed. The NMI pin triggers an

exception on its falling edge.

13.1.1 Non-Maskable Interrupt Processing

At reset, NMI interrupts are disabled and must remain disabled until software initializes the interrupt table,

interrupt base register (INTBASE), and the interrupt mode. The external NMI interrupt is enabled by

setting the EXNMI.ENLCK bit and will remain enabled until a reset occurs. Alternatively, the external NMI

interrupt can be enabled by setting the EXNMI.EN bit and will remain enabled until an NMI interrupt or a

reset occurs.

13.2 Maskable Interrupts

The IRQn interrupt channels are level-sensitive. Any edge sensitivity must be implemented at the interrupt

source. The IRQ interrupts are enabled and disabled by the E and I bits in the PSR register. Both bits

must be set to enable maskable interrupts. The EI and DI instructions are used to set (enable) and clear

(disable) the E bit.

Each interrupt source can be individually enabled or disabled under software control through the IENR

13.2.1 Maskable Interrupt Processing

The IVECT register holds the interrupt vector number of the enabled and pending interrupt with the

highest priority, mapped to the range 10h to 56h. IRQ0 is mapped to 10h, while IRQ70 is mapped to 56h.

The CPU performs an interrupt acknowledge bus cycle on receiving a maskable interrupt request from the

ICU. During the interrupt acknowledge cycle, a byte is read from address FF FE00h (the IVECT register).

The byte is used as an index into the Dispatch Table to determine the address of the interrupt handler.

Because IRQ0 is not connected to any interrupt source, the interrupt vector number 10h should not be

generated. However, an entry should be provided for this vector in the dispatch table that points to a

default interrupt handler. One possible condition in which this vector number may occur is deassertion of

an interrupt at its source before the interrupt controller generates an interrupt acknowledge cycle.

13.2.2 Maskable Interrupt Sources

Table 13-1 shows the interrupt sources assigned to the maskable interrupts.

Table 13-1. Maskable Interrupts Assignment

IRQn

DESCRIPTION

ASC CHANNEL

IRQ70

RTI (Timer 0)

IRQ69

Real-Time Clock

IRQ68

Bluetooth LLC 0

Interrupts

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