CP3SP33SMSSLASHNOPB datasheet(102/407 Pages) TI1

102 / 407 page

CP3SP33

SNOSCW5 – MAY 2013

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HALT

The Halt Mode bit indicates whether the device is in Halt mode. If the WBPSM bit is clear and

the device is in Power Save mode, writing 1 to the HALT bit causes the device to start the

switch to Halt mode. If the WBPSM bit is set when the HALT bit is written with 1, entry into

Halt mode is delayed until execution of a WAIT instruction. When in Halt mode, the PMM

stops HCLK Clock and then turns off the high-frequency oscillator and PLLs. The low-

frequency oscillator also may be stopped in Halt mode by setting the PMMSTCTL.DSC bit.

The HALT bit can be set and cleared by software. Halt mode is exited by a hardware wake-up

event. When this signal is set high, the oscillator is started. After the oscillator has stabilized,

the HALT bit is cleared by hardware. When set, the HALT bit overrides the IDLE and PSM

bits.

0 – Device is not in Halt mode.

1 – Device is in Halt mode.

WBPSM

When the Wait Before Power Save Mode bit is clear, a switch from Active mode to Power

Save mode only requires setting the PSM bit. When the WBPSM bit is set, a switch from

Active mode to Power Save, Idle, or Halt mode is performed by setting the PSM, IDLE, or

HALT bit, respectively, and then executing a WAIT instruction. Also, if the DMC or DPLLC bits

are set, the high-frequency oscillator or PLLs may be disabled only after a WAIT instruction is

executed and the Power Save, Idle, or Halt mode is entered.

0 – Mode transitions may occur immediately.

1 – Mode transitions are delayed until the next WAIT instruction is executed.

DMC

The Disable Main Clock bit may be used to disable Main Clock and the high-frequency

oscillator in Power Save and Idle modes. In Active mode, Main Clock is enabled without

regard to the DMC value. In Halt mode, Main Clock is disabled without regard to the DMC

value. Disabling Main Clock will also disable the PLL Clocks. The DMC bit is cleared by

hardware when a hardware wake-up event is detected.

0 – Main Clock is only disabled in Halt mode or when disabled by the HCC mechanism.

1 – Main Clock is also disabled in Power Save and Idle modes, unless Slow Clock is

generated from Main Clock or PLL Clock.

HCCM

The Hardware Clock Control for Main Clock bit may be used in Power Save and Idle modes to

disable Main Clock and the high-frequency oscillator conditionally, depending on whether the

Bluetooth LLC is in Sleep mode. Disabling Main Clock has the side-effect of disabling the PLL

Clocks. The DMC bit must be clear for this mechanism to operate. The HCCM bit is

automatically cleared when the device enters Active mode.

0 – Main Clock is disabled in Power Save or Idle mode only if the DMC bit is set.

1 – Main Clock is also disabled if the Bluetooth LLC is idle.

WACK

The Wake-Up on Interrupt Acknowledge bit is set to enable a mode in which the system will

wake up when an interrupt acknowledge occurs. This could be used in Power Save mode

without using the WAIT instruction, so that an interrupt could be used to power up the system

quickly, rather than needing the software to do it. If the WACK bit is clear, then an interrupt

acknowledge will not cause a wake up from a low power mode.

0 – Interrupt acknowledge does not wake up from low-power mode.

1 – Interrupt acknowledge wakes up from low-power mode.

DSC

The Disable Slow Clock bit is used to disable the low-frequency oscillator in Halt mode. This

bit would typically be set for maximum power savings, but the low-frequency oscillator is

optimized for very low power so it may not be necessary to disable it. Leaving the oscillator

running avoids a start-up delay for the low-frequency oscillator. The DSC bit is cleared when a

hardware wake-up event occurs.

0 – Low-frequency oscillator is not disabled.

1 – Low-frequency oscillator is disabled when Halt mode is entered.

102

Power Management Module

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