CP3SP33SMSSLASHNOPB datasheet(53/407 Pages) TI1

53 / 407 page

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

Freeze mode can be entered by setting the FREEZE bit in the MCFG register or using a mechanism

enabled through the Serial Debug Interface (SDI). Freeze mode does not directly affect the DSP

subsystem.

NOTE

Debugging tools may assert Freeze mode to gather information, which may cause periodic

fluctuations in response (bus availability, interrupt latency, etc.). Anomalous behavior often

may be traced to the activity of these tools.

11.3 System Configuration Registers

The system configuration registers control and provide status for certain aspects of device setup and

operation, such as indicating the states sampled from the ENV[1:0] inputs. The system configuration

registers are listed in Table 11-3.

Table 11-3. System Configuration Registers

NAME

ADDRESS

DESCRIPTION

MCFG

FF F400h

Module Configuration Register

MSTAT

FF F404h

Module Status Register

SWRESET

FF F408h

Software Reset Register

SYSCFG

FF F40Ch

System Configuration Register

11.4 Module Configuration Register (MCFG)

The MCFG register is a byte-wide, read/write register that selects the clock output features of the device

and enables Freeze mode. The MCFG register format is shown below. At reset, the MCFG register is

initialized to 00h.

Reserved

FREEZE

Reserved

ENV1SEL

ENV0SEL

ENV1OE

ENV0OE

The ENV0 Output Enable bit enables driving an internal clock signal selected by the

ENV0SEL bit on the ENV0 pin. If no signal is driven on the ENV0 pin, it will be undriven

(high impedance) after reset.

0 – ENV0 is undriven after reset.

1 – ENV0 is driven by an internal clock signal.

ENV1OE

The ENV1 Output Enable bit enables driving an internal clock signal selected by the

ENV1SEL bit on the ENV1 pin. If no signal is driven on the ENV1 pin, it will be undriven

(high impedance) after reset.

0 – ENV1 is undriven after reset.

1 – ENV1 is driven by an internal clock signal.

ENV0SEL

The ENV0 Select bit selects an internal clock signal to be available for driving on the ENV0

pin. The ENV0OE bit must be set to enable driving the selected signal on the ENV0 pin.

0 – Slow Clock is available to drive on ENV0.

1 – PLL1 Clock is available to drive on ENV0.

ENV1SEL

The ENV1 Select bit selects an internal clock signal to be available for driving on the ENV1

pin. The ENV1OE bit must be set to enable driving the selected signal on the ENV1 pin.

0 – Main Clock is available to drive on ENV1.

1 – PLL2 Clock is available to drive on ENV1.

System Configuration

Submit Documentation Feedback

Product Folder Links :CP3SP33

CP3SP33SMS/NOPB датащи(PDF) 53 Page - Texas Instruments

CP3SP33SMS/NOPB датащи(HTML) 53 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL