CP3SP33SMSSLASHNOPB datasheet(77/407 Pages) TI1

77 / 407 page

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

INTGPB2

The Interrupt Priority Group B bits specify the most significant bit for selecting one of four

interrupt priority groups.

0 – Interrupt belongs to group 0 or 1.

1 – Interrupt belongs to group 2 or 3.

13.6.19 Interrupt Debug Register (IDBG)

The IDBG register is a 32-bit, read-only register. Fields in this register indicate the interrupt number of the

highest priority currently asserted interrupt and the interrupt number returned to the CPU during the last

interrupt acknowledge cycle. (These may differ if a higher-priority interrupt is asserted after the interrupt

acknowledge cycle.) The register is initialized to 0000 0000h at reset.

16 15

8 7

Reserved

IRQVECT

INTVECT

The INTVECT field indicates the interrupt vector number of the highest priority currently

asserted interrupt.

IRQVECT

The IRQVECT field indicates the interrupt vector number returned to the CPU during the last

interrupt acknowledge cycle.

13.7 Usage Notes

The recommended initialization sequence is:

1. Initialize the INTBASE register of the CPU.

2. Prepare the interrupt routines of the relevant interrupts.

3. Set up the interrupt conditions in the peripherals.

4. Set the relevant bits in the interrupt enable/mask registers (IENRn).

5. Set the I bit in the PSR.

Clearing an interrupt request before it is serviced can cause a spurious interrupt, (i.e., the CPU detects an

interrupt not reflected by IVECT). Software must clear interrupt requests only after interrupts are disabled.

Clearing any of the interrupt enable bits should be performed while the I bit in the PSR register is clear.

14 Clock Generation

The clock circuitry includes oscillators for generating a 12MHz Main Clock and an optional 32.768-kHz

Slow Clock from external crystal networks. Alternatively, either clock may be replaced by an external clock

source.

Two identical PLLs are available to provide higher clock frequencies (up to 96 MHz) using Main Clock as

a reference frequency. The PLLs also may be used to synchronize with an external clock driven on the

I2S interface (I2SCLK).

Most of the functional blocks of the device operate from one of the global clocks generated by this

module:

•

Main Clock—12-MHz clock generated by an on-chip oscillator or received from an external clock

source.

•

PLL1 Clock—clock synthesized by PLL1 from Main Clock or the external I2SCLK clock input.

•

PLL2 Clock—clock synthesized by PLL2 from Main Clock or the external I2SCLK clock input.

•

HCLK Clock—clock used by the CPU and devices on the CPU core AHB bus. HCLK Clock is

generated by a prescaler from Main Clock, PLL1 Clock, or PLL2 Clock. Available prescale factors are

1 to 2048 in increments of 1/2 clock period. In Power Save mode, HCLK Clock is driven by Slow Clock.

•

PCLK Clock—clock used by devices on the peripheral APB bus. PCLK Clock is generated by a

prescaler from HCLK Clock. Available prescale factors are 1, 2, and 4.

Clock Generation

Submit Documentation Feedback

Product Folder Links :CP3SP33

CP3SP33SMS/NOPB датащи(PDF) 77 Page - Texas Instruments

CP3SP33SMS/NOPB датащи(HTML) 77 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL