CP3SP33SMSSLASHNOPB datasheet(30/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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When a cache hit occurs while the cache is locked, the cache data is passed to the CPU, and the PLRU

bits are up-dated. However, the PLRU bits have no effect while the cache is locked, because no new

cache entries are allocated.

7.2

Cache Invalidation

The cache does not snoop any bus cycles. Software is responsible for invalidating the cache when the

CPU or any other device writes to program memory. The cache is invalidated by executing the CINV [i]

instruction. This clears the valid bits for all of the cache entries.

The cache is automatically invalidated at reset and when it is disabled.

CPU Core Bus Arbitration

The CPU core AHB bus can be controlled by either of two bus masters:

•

CPU Core

•

CPU DMA Controller

The bus arbiter implements two levels of priority arbitration among the potential bus masters:

•

Group Priority—each potential bus master is assigned to one of four priority groups. The priority

among groups is linear, with group A at highest priority and group D at lowest priority.

•

Priority within a Group—either of two arbitration policies may be selected for a group: linear priority and

round-robin. Linear priority gives bus ownership to the requesting device with the lowest master

number. Round-robin assigns bus ownership in a cyclic sequence (for example, 2-3-4-2-3-4) among

requesting devices.

Group priority is always considered before priority within a group. Priority within a group is only considered

after the group is selected.

With only two potential bus masters, the bus arbitration mechanism may seem excessively complex,

however this architecture is designed for scalability to future devices which may have a greater number of

potential bus masters.

The default register settings for the bus arbiter provide an efficient arbitration policy across a wide range of

applications:

•

One Group—all potential bus masters are assigned to group A.

•

Round-Robin Arbitration—a round-robin policy avoids starving any potential bus master of bandwidth.

•

Default Bus Master is CPU—when no potential bus master asserts a request for control of the bus, the

CPU is given ownership of the bus. This avoids stalling the CPU when it needs to access an idle bus.

When a linear priority policy is selected for a priority group, the master number is used to resolve

arbitration among devices within that group, with lower numbers receiving higher priority. Table 8-1 shows

the assignment of master numbers.

Table 8-1. Master Number Assignment

POTENTIAL BUS MASTER

MASTER NUMBER

CPU

CPU DMA Controller

Whether or not any default settings are changed, software should lock the bus arbiter configuration during

system initialization by writing 1 to the LOCK bit in the ARBCFGLK register.

CPU Core Bus Arbitration

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