CP3SP33SMSSLASHNOPB datasheet(71/407 Pages) TI1

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DS430

INTGPBR

INTGPAR

IRQ5

IRQ1

Group 3

Group 2

IRQ3

IRQ4

Group 1

IRQ6

IRQ2

Group 0

Increasing Channel Priority

CP3SP33

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SNOSCW5 – MAY 2013

For example, if INTGPAR6:1 is loaded with 011101b and INTGPBR6:1 is loaded with 010001b, the priority

groups for these interrupts are assigned as shown in Figure 13-1.

Figure 13-1. Interruupt Priority Groups

If the six IRQ1 through IRQ6 interrupts are asserted, then IRQ6 is taken because this interrupt belongs to

the highest priority group (lowest group number), and it has the highest channel number within that group.

If only IRQ1 and IRQ5 are asserted, then IRQ5 is taken because this is the highest priority interrupt in

group 3 and there are no asserted interrupts in other groups.

13.4 Nested Interrupts

Nested NMI interrupts are permanently enabled when the ENLCK bit in the EXNMI register is used to

enable NMI interrupts. When nesting is not desired, the EN bit may be set to enable one occurrence of the

NMI interrupt, after which NMI interrupts are disabled until the EN bit is set again.

Nested maskable interrupts are disabled by default, because the I bit in the PSR is automatically cleared

when the interrupt is acknowledged. An interrupt handler can allow nested maskable interrupts by setting

the I bit using the LPR instruction.

Nesting of specific maskable interrupts can be selectively enabled or disabled using the IENR register,

before setting the I bit. Any number of levels of nested interrupts are allowed, limited only by the available

memory for the interrupt stack.

13.5 Software Interrupts

Setting a bit in the SOFTR register requests the corresponding maskable interrupt. The request stays

active until the bit is cleared by software or a device reset. Software interrupt requests are maskable in the

IENR registers, and active interrupts (from either hardware or software sources) are indicated in the ISTR

13.6 Interrupt Controller Registers

Table 13-3 lists the interrupt controller registers.

Interrupts

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