CP3SP33SMSSLASHNOPB datasheet(88/407 Pages) TI1

88 / 407 page

CP3SP33

SNOSCW5 – MAY 2013

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14.8.1 Clock and Reset Control Register (PMMCKCTL)

The PMMCKCTL register is a byte-wide, read/write register that controls the clock selection and contains

the power-on reset status bit. At reset, the PMMCKCTL register is initialized as described below:

5 4

Reserved

FCLKSRC

SCLK

Reserved

POR

The Power-On-Reset bit is set when a power-on condition has been detected. This bit can

only be cleared by software, not set. Writing a 1 to this bit will be ignored, and the previous

value of the bit will be unchanged.

0 – Software cleared this bit.

1 – Software has not cleared his bit since the last reset.

SCLK

The Slow Clock Select bit controls the clock source used for the Slow Clock. If set while

the low-frequency oscillator is not stable, this bit will read as 1 but the clock source will not

switch until the low-frequency oscillator is stable. This bit cannot be cleared while the high-

frequency oscillator is not stable. At reset, this bit is cleared.

0 – Slow Clock driven by prescaled Main Clock.

1 – Request asserted to drive Slow Clock from the 32.768 kHz oscillator.

FCLKSRC

The Fast Clock Source field selects the clock source used to generate HCLK Clock. After

reset, the Main Clock is selected. Requesting a switch to a PLL Clock while the

corresponding PMMPLLn.CTL2.PLLCLKSTB bit is clear (PLL Clock not stable) will be

stalled until the PLL Clock is stable. When switching between PLL Clocks, there must be

an intermediate step in which Main Clock is selected. At reset, this field is initialized to 11b.

00 – PLL1.

01 – PLL2.

10 – Reserved.

11 – Main Clock.

14.8.2 Clock Status Register (PMMSR)

The PMMSR register is a byte-wide read-only register that holds the two bits which indicate whether the

high-frequency oscillator and the low-frequency oscillator are stable.

Reserved

MCLKSTB

SCLKSTB

The Slow Clock Stable bit indicates whether the low-frequency oscillator is producing a

stable clock.

0 – Low-frequency oscillator is unstable, disabled, or not oscillating.

1 – Low-frequency oscillator is available.

MCLKSTB

The Main Clock Stable bit indicates whether the high-frequency oscillator is producing a

stable clock.

0 – High-frequency oscillator is unstable, disabled, or not oscillating.

1 – High-frequency oscillator is available.

14.8.3 HCLK Clock Prescaler Register (PMMPRSHC)

The PMMPRSHC register is a 16-bit read/write register that holds the 12-bit prescaler available to

generate HCLK Clock. The register is initialized to 001Fh at reset.

12M M11

Reserved

HPHCLK

Clock Generation

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