CP3SP33SMSSLASHNOPB datasheet(73/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

Reserved

ENLCK

The EXNMI trap enable bit is one of two bits that can be used to enable NMI interrupts. The bit

is cleared by hardware at reset and whenever the NMI interrupt occurs (EXNMI.EXT set). It is

intended for applications where the NMI input toggles frequently but nested NMI traps are not

desired. For these applications, the EN bit needs to be re-enabled before exiting the trap

handler. When used this way, the ENLCK bit should never be set. The EN bit can be set and

cleared by software (software can set this bit only if EXNMI.EXT is cleared), and should only be

set after the interrupt base register and the interrupt stack pointer have been set up.

0 – NMI interrupts not enabled by this bit (but may be enabled by the ENLCK bit).

1 – NMI interrupts enabled.

The PIN bit indicates the state (non-inverted) on the NMI input pin. This bit is read-only, data

written into it is ignored.

0 – NMI pin not asserted.

1 – NMI pin asserted.

ENLCK

The EXNMI trap enable lock bit is used to permanently enable NMI interrupts. Only a device

reset can clear the ENLCK bit. This allows the external NMI feature to be enabled after the

interrupt base register and the interrupt stack pointer have been set up. When the ENLCK bit is

set, the EN bit is ignored.

0 – NMI interrupts not enabled by this bit (but may be enabled by the EN bit).

1 – NMI interrupts enabled.

13.6.4 Interrupt Enable and Mask Register 0 (IENR0)

The IENR0 register is a 32-bit, read/write register which holds bits that individually enable and disable the

maskable interrupt sources IRQ1 to IRQ31. The register is initialized to 0000 0000h at reset.

IEN0

Reserved

IEN0

Each Interrupt Enable bit enables or disables the corresponding interrupt channels IRQ1 through

IRQ31. Because IRQ0 is not used, bit 0 is ignored.

0 – Interrupt is disabled.

1 – Interrupt is enabled.

13.6.5 Interrupt Enable and Mask Register 1 (IENR1)

The IENR1 register is a 32-bit, read/write register which holds bits that individually enable and disable the

maskable interrupt sources IRQ63 to IRQ32. The register is initialized to 0000 0000h at reset.

IEN1

Each Interrupt Enable bit enables or disables the corresponding interrupt channels IRQ32

through IRQ63.

0 – Interrupt is disabled.

1 – Interrupt is enabled.

13.6.6 Interrupt Enable and Mask Register 2 (IENR2)

The IENR2 register is a 32-bit, read/write register which holds bits that individually enable and disable the

maskable interrupt sources IRQ70 to IRQ64. Only bits 6:0 of this register are used. The register is

initialized to 0000 0000h at reset.

Interrupts

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