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CP3SP33SMS/NOPB датащи(PDF) 41 Page - Texas Instruments |
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CP3SP33SMS/NOPB датащи(HTML) 41 Page - Texas Instruments |
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41 / 407 page ![]() CP3SP33 www.ti.com SNOSCW5 – MAY 2013 WFEI The Write FIFO Empty Indicator bit is asserted when the write FIFO is empty. 0 – FIFO is not empty. 1 – FIFO is empty. PSEMI The Peripheral Semaphore Access Indicator bit is set when a bit in the APBP_SEM register has been set by the DSP and the corresponding bit in the PMASK register is clear. 0 – No unmasked semaphore bit is set. 1 – An unmasked semaphore bit is set. PRI0 The Reply Register 0 Indicator bit is set when the DSP writes the APBP_REP0 register. The RRI0 bit is cleared when the CPU reads the APBP_REP0 register. 0 – APBP_REP0 has not been written. 1 – APBP_REP0 was written but not read. RRI1 The Reply Register 1 Indicator bit is set when the DSP writes the APBP_REP1 register. The RRI1 bit is cleared when the CPU reads the APBP_REP1 register. 0 – APBP_REP1 has not been written. 1 – APBP_REP1 was written but not read. RRI2 The Reply Register 2 Indicator bit is set when the DSP writes the APBP_REP2 register. The RRI2 bit is cleared when the CPU reads the APBP_REP2 register. 0 – APBP_REP2 has not been written. 1 – APBP_REP2 was written but not read. RCOMIM0 The Read Command Register 0 Indicator bit is set when the CPU writes the APBP_COM0 register. The RCOMIM0 bit is cleared when the DSP or CPU reads the APBP_COM0 register. 0 – APBP_COM0 has not been written. 1 – APBP_COM0 was written but not read. RCOMIM1 The Read Command Register 1 Indicator bit is set when the CPU writes the APBP_COM1 register. The RCOMIM1 bit is cleared when the DSP or CPU reads the APBP_COM1 register. 0 – APBP_COM1 has not been written. 1 – APBP_COM1 was written but not read. RCOMIM2 The Read Command Register 2 Indicator bit is set when the CPU writes the APBP_COM2 register. The RCOMIM2 bit is cleared when the DSP or CPU reads the APBP_COM2 register. 0 – APBP_COM2 has not been written. 1 – APBP_COM2 was written but not read. 9.3.7 CPU-to-DSP Semaphore Register (PSEM) The PSEM register is a 16-bit, read/write register used by the CPU to assert an interrupt to the DSP. If a bit in this register is set and the corresponding bit in the APBP_MASK register (only visible to the DSP) is clear, the DSP is interrupted. After reset, this register is clear. 15 1 PSEM Copyright © 2013, Texas Instruments Incorporated DSP and Audio Peripherals 41 Submit Documentation Feedback Product Folder Links :CP3SP33 |
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