CP3SP33SMSSLASHNOPB datasheet(65/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

Reserved

DIR

TCS

DTO

EOVR

ETC

CHEN

WMODE

INCB

ADB

INCA

ADA

SWRQ

Reserved

DIR

TCS

DTO

EOVR

ETC

CHEN

12M M11

Reserved

SRCRQ

CHEN

The Channel Enable bit must be set to enable any DMA operation on this channel. Writing a

1 to this bit starts a new DMA transfer even if it is currently a 1. If all DMACNTn.CHEN bits

are clear, the DMA clock is disabled to reduce power.

0 – Channel disabled.

1 – Channel enabled.

ETC

If the Enable Interrupt on Terminal Count bit is set, it enables an interrupt when the

DMASTAT.TC bit is set.

0 – Interrupt disabled.

1 – Interrupt enabled

EOVR

If the Enable Interrupt on OVR bit is set, it enables an interrupt when the DMASTAT.OVR bit

is set.

0 – Interrupt disabled.

1 – Interrupt enabled.

ETO

If the Enable Interrupt on Timeout bit is set, it enables an interrupt when the DMASTAT.TO

bit is set.

0 – Interrupt disabled.

1 – Interrupt enabled.

TCS

The Transfer Cycle Size bit specifies the number of bytes transferred in each DMA transfer

cycle. This bit will be overridden if the WMODE bit is set.

0 – Byte transfers (8 bits per cycle).

1 – Word transfers (16 bits per cycle).

DIR

The Transfer Direction bit specifies the direction of the transfer relative to Device A.

0 – Device A (addressed by the ADCAn register) is the source.

1 – Device A is the destination

The Operation Type bit specifies the operation mode of the DMA controller.

0 – Single-buffer mode or double-buffer mode enabled.

1 – Auto-Initialize mode enabled.

SWRQ

The Software DMA Request bit is written with a 1 to initiate a software DMA request. Writing

a 0 to this bit deactivates the software DMA request. The SWRQ bit must only be written

when the peripheral DMA requests for the channel are disabled and the channel is inactive

(DMASTAT.CHAC = 0).

0 – Software DMA request is inactive.

1 – Software DMA request is active.

ADA

If the Device A Address Control bit is set, it enables updating the Device A address.

0 – ADCAn address unchanged.

1 – ADCAn address incremented or decremented, as controlled by the INCA field and

WMODE and TCS bits.

INCA

The Increment/Decrement ADCAn field together with the WMODE and TCS bits control the

step size for the Device A address increment/decrement.

CPU DMA Controller

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