CP3SP33SMSSLASHNOPB datasheet(89/407 Pages) TI1

89 / 407 page

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

HPHCLK

The Half Periods High Frequency Clock field holds the divisor (expressed in half-periods of

the input clock source) for the prescaler used to generate HCLK Clock. The clock source is

divided by ((HPHCLK + 1) ÷ 2) to obtain the HCLK Clock. The field is biased by 1, so the

default value of this field specifies 32 half-periods, which is a divisor of 16. Zero is an

undefined value for this field.

14.8.4 PCLK Clock Prescaler Register (PMMPRSPC)

The PMMPRSPC register is a byte-wide, read/write register that holds the divisor for generating PCLK

Clock from HCLK Clock. The maximum PCLK Clock frequency is 48 MHz. The register is initialized to 00h

at reset.

2M 1

Reserved

DIVPCLK

The Divisor PCLK Clock field has four defined values:

00b – ÷1

01b – ÷2

10b – ÷4

11b – Reserved.

14.8.5 Slow Clock Prescaler Register (PMMPRSSC)

The PMMPRSSC register is a 16-bit, read/write register that holds the 14-bit prescaler available to

generate Slow Clock from Main Clock. The register is initialized to 02DBh at reset.

14M 13

Reserved

HPSCLK

The Half Periods Slow Clock field holds the divisor (expressed in half-periods of the input

clock source) for the prescaler used to generate Slow Clock. The Main Clock is divided by

((HPSCLK + 1) ÷ 2) to obtain the Slow Clock. At reset, the HPSCLK register is initialized to

02DBh, which generates a Slow Clock rate of 32.786885 kHz. This is about 0.5% faster

than a Slow Clock generated from an external 32.768 kHz crystal network. Zero is an

undefined value for this field.

14.8.6 PLLn Control Register 1 (PMMPLLnCTL1)

The PMMPLLnCNT1 registers are 16-bit, read/write registers that hold control fields for the corresponding

PLL. The registers are initialized to 00h at reset.

5 4

Reserved

PLLIPSEL

PLLDCOE

PLLEN

The PLL Enable field controls whether the PLL is enabled or disabled. Before software can

power down a PLL used to generate HCLK Clock or an Auxiliary Clock, the clocks must be

switched to another clock source.

00 – PLL disabled.

01 – PLL enabled.

10 – Reserved.

11 – Reserved.

PLLDCOE

The PLL Direct Clock Output Enable bit controls the corresponding PLL output. The PLL

Clock output is driven only when this bit is set and the PLL Clock is stable.

0 – PLL Clock output disabled.

1 – PLL Clock is enabled when stable.

Clock Generation

Submit Documentation Feedback

Product Folder Links :CP3SP33

CP3SP33SMS/NOPB датащи(PDF) 89 Page - Texas Instruments

CP3SP33SMS/NOPB датащи(HTML) 89 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL