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CP3SP33SMS/NOPB датащи(PDF) 8 Page - Texas Instruments

номер детали CP3SP33SMS/NOPB
подробное описание детали  Connectivity Processor with Cache, DSP, and Bluetooth짰, USB, and Dual CAN Interfaces
PDF  407 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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CP3SP33SMS/NOPB датащи(HTML) 8 Page - Texas Instruments

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CP3SP33
SNOSCW5 – MAY 2013
www.ti.com
The 32K bytes of CPU RAM are used for temporary storage of data and for the program stack and
interrupt stack. Read and write operations can be byte-wide or word-wide, depending on the instruction
executed by the CPU.
3.6
Bluetooth LLC
The integrated hardware Bluetooth Lower Link Controller (LLC) complies to the Bluetooth Specification
Version 1.2 and integrates the following functions:
7K-byte dedicated Bluetooth data RAM
1K-byte dedicated Bluetooth sequencer RAM
Support of all Bluetooth 1.2 packet types and extended Synchronous Connection-Oriented (eSCO)
links
Support for fast frequency hopping of 1600 hops/s
Access code correlation and slot timing recovery circuit
Power Management Control Logic
BlueRF-compatible interface (mode 2/3) to connect with National’s LMX5252 and other RF transceiver
chips
3.7
USB
The full-speed Universal Serial Bus (USB) node and host controller is compatible with USB Specification
2.0 and USB On-The-Go. It integrates the required USB transceiver, the Serial Interface Engine (SIE), and
USB endpoint FIFOs. A total of seven endpoint pipes are supported: one bidirectional pipe for the
mandatory control EP0 and an additional six pipes for unidirectional endpoints to support USB interrupt,
bulk, and isochronous data transfers.
The on-chip USB transceiver features an integrated pullup resistor on the D+ line to UVCC. This pullup
resistor can be switched in or out by the USB VBUS sense input (VBUS), which eliminates the need for
external components.
3.8
CAN Interface
The two CAN modules support Full CAN 2.0B class, CAN serial bus interfaces for applications that require
a highspeed (up to 1 Mbits per second) or a low-speed interface with CAN bus master capability. The data
transfer between CAN and the CPU is established by 15 memory-mapped message buffers, which can be
individually configured as receive or transmit buffers. An incoming message is filtered by two masks, one
for the first 14 message buffers and another one for the 15th message buffer to provide a basic CAN path.
A priority decoder allows any buffer to have the highest or lowest transmit priority. Remote transmission
requests can be processed automatically by automatic reconfiguration to a receiver after transmission or
by automated transmit scheduling upon reception. In addition, a 16-bit time stamp counter supports real-
time applications.
The CAN modules allow single-cycle byte or word read/ write access. A set of diagnostic features (such as
loopback, listen only, and error identification) support the development with the CAN modules and provide
a sophisticated error management tool.
The CAN receivers can trigger a wake-up condition out of low-power modes through the Multi-Input Wake-
Up unit.
8
Device Overview
Copyright © 2013, Texas Instruments Incorporated
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Product Folder Links :CP3SP33



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