CP3SP33SMSSLASHNOPB datasheet(90/407 Pages) TI1

90 / 407 page

CP3SP33

SNOSCW5 – MAY 2013

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PLLIPSEL

The PLL Input Select field selects the input clock source for the corresponding PLL.

00 – Main Clock.

01 – I2SCLK pin.

10 – Reserved.

11 – Reserved

14.8.7 PLLn Control Register 2 (PMMPLLnCTL2)

The PMMPLLnCNT2 registers are 16-bit, read/write registers that hold control fields for the corresponding

PLL. The registers are initialized to 00h at reset.

Reserved

HCCPLL

DPLLC

PLLCLKSTB

The PLL Clock Stable bit indicates when the corresponding PLL Clock is stable.

0 – PLL Clock not stable.

1 – PLL Clock is stable.

DPLLC

The Disable PLL Clock Enable bit controls whether the corresponding PLL is disabled

when entering the Power Save or Idle modes. This bit is cleared when a hardware wake-

up event occurs.

0 – PLL may be enabled in Power Save and Idle modes.

1 – PLL is always disabled in Power Save and Idle modes.

HCCPLL

The Hardware Clock Control PLL bit enables the hardware clock control mechanism,

See Section 16.5 for more information.

0 – Hardware clock control disabled.

1 – Hardware clock control enabled.

14.8.8 PLLn M Divider Register (PMMPLLnMDIV)

The PMMPLLnMDIV registers are byte-wide, read/write registers that hold the 8-bit M divisor for the

corresponding PLL. The registers are initialized to 00h at reset.

MDIV

The M Divisor field specifies an integer divisor. See Section 14.4.1 for more information.

14.8.9 PLLn N Divider Register (PMMPLLnNDIV)

The PMMPLLnNDIV registers are byte-wide, read/write registers that hold the 8-bit integer part of the N

divisor. The registers are initialized to 00h at reset.

NDIV

The N Divisor field specifies the integer part of the N divisor. See Section 14.4.1 for more

information.

14.8.10 PLLn N Mod Register (PMMPLLnNMOD)

The PMMPLLnNMOD registers are 16-bit, read/write registers that hold the 5-bit fractional part of the N

divisor for the corresponding PLL and a control field for the level of dithering in effect. The registers are

initialized to 00h at reset.

14 13

8 7

NMOD_DITH

Reserved

NMOD

Clock Generation

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