CP3SP33SMSSLASHNOPB datasheet(32/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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8.1.4

Arbiter Configuration Lock Register (ARBCFGLK)

The ARBALGO register is a 32-bit, read/write register that is used to lock the bus arbiter configuration.

When the configuration is locked, writes to the bus arbiter registers are ignored. Reads are unaffected.

Once locked, the configuration may not be unlocked until the device is reset. After reset, this register is

initialized to 0000 0000h.

Reserved

LOCK

The Lock bit controls whether the bus arbiter registers are locked.

0 – Unlocked.

1 – Locked.

DSP and Audio Peripherals

The CP3SP33 includes a Teak DSP for supporting high-performance audio applications. DSP software

packages are available from Texas Instruments for signal processing operations commonly used to

process audio data.

The DSP implements 16-bit fixed-point arithmetic with a 4bus (X, Y, Z, and Program) Harvard architecture.

The fast DSP core (96 MHz) and large on-chip 24K-byte program and 24K-byte data memories satisfy a

wide range of compute-intensive applications. The DSP has a 32-bit high-bandwidth bus separate from

that of the CPU, and it has an independent DMA controller, for efficient bus utilization.

The CPU host has a register-based interface for controlling the DSP and accessing the DSP program and

data memory space. The CPU can reset the DSP, interrupt the DSP, and assert a DSP DMA request. The

DSP can assert an interrupt request to the CPU, and it can wake the CPU from a low-power mode.

Figure 9-1 shows the architecture of the DSP and audio peripherals. The DSP DMA controller is a slave

on the CPU APB bus, so that the CPU host can use a DMA channel for downloading software to the DSP

program and data memories. Once released to begin execution, the DSP is bus master on its own 32-bit,

high-bandwidth bus, which the DSP uses to access three types of slave devices:

•

4K-byte Shared RAM—data memory which is mapped into CPU and DSP address spaces.

•

External Bus Interface—interface to external (off-chip) memory devices.

•

Shared Audio Peripheral APB Bus—peripherals shared between the CPU and DSP (codec, I2S

interface, etc.).

The Audio Subsystem Controller (ASC) provides multiplexing of interrupt and DMA signals between

shared peripherals and the independent interrupt and DMA controllers of the CPU and DSP.

DSP and Audio Peripherals

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