CP3SP33SMSSLASHNOPB datasheet(98/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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The PLLs and the high-frequency oscillator may be disabled as controlled by register bits. The low-

frequency oscillator remains active. The Power Management Module (PMM) and the Timing and

Watchdog Module (TWM) continue to operate from the Slow Clock. The auxiliary clocks can be turned off

under software control before switching to a low-power mode, or they remain active as long as they have

active

clock

source

(Main

Clock,

PLL1

Clock,

PLL2

Clock,

selected

the

PMMCKCTL.FCLKSRC bit). Alternatively, generation of Main Clock and the PLL Clocks can be controlled

by the Bluetooth controller through the Hardware Clock Control function (described in Section 16.5), if

enabled.

16.4 Halt Mode

In Halt mode, all the device clocks, including the Main Clock, PLL1 Clock, PLL2 Clock, HCLK Clock, PCLK

Clock, and Slow Clock, are disabled. Halt mode is intended for applications in which an external wake-up

signal can be used to power-up the system through the RESET input or an MIWU input.

The high-frequency oscillator and PLLs are turned off. This is the only mode in which the low-frequency

oscillator may be disabled, however its circuitry is optimized to ensure lowest possible power

consumption. This mode allows the device to reach the absolute minimum power consumption without

losing its state (memory, registers, etc.).

16.5 Hardware Clock Control

The Hardware Clock Control (HCC) mechanism gives the Bluetooth Lower Link Controller (LLC) individual

control over the high-frequency oscillator and the PLLs. The Bluetooth LLC can enter a Sleep mode for a

specified number of low-frequency clock cycles. While the Bluetooth LLC is in Sleep mode and the

CP3SP33 is in Power Save or Idle mode, the HCC mechanism may be used to control whether the high-

frequency oscillator or PLLs are powered.

The PMMSTCTL.HCCM bit enables control by the Bluetooth LLC over the high-frequency oscillator, and

the PMMPLLnCTL2.HCCPLL bits enable control over the corresponding PLLs. If the HCCM bit is set, then

control is enabled over both the high-frequency oscillator and the PLLs, and the HCCPLL bits are ignored.

(The PLLs cannot be enabled while the high-frequency oscillator is disabled.)

Altogether, three mechanisms control whether the high-frequency oscillator is active, and four

mechanisms control whether the PLLs are active:

•

HCC bits—the HCC bits (PMMSTCTL.HCCM and PMMPLLnCTL2.HCCPLL) allow the Bluetooth LLC

to disable the high-frequency oscillator and PLLs during Power Save and Idle modes when the

Bluetooth LLC goes into Sleep mode. The HCC bits are automatically cleared when Active mode is

entered.

•

Disable bits—the disable bits (PMMSTCTL.DMC and PMMPLLnCTL2.DPLLC) force the high-

frequency oscillator and PLLs to be disabled when entering the Power Save and Idle modes. When

set, these bits override the HCC mechanism. The DMC and DPLLC bits are automatically cleared by a

hardware wake-up event.

•

Power Management Mode—Halt mode disables the high-frequency oscillator and PLLs, without regard

to any register bits. Active mode enables the high-frequency oscillator, again without regard to any bits.

Entering Active mode will restart any PLLs enabled to run.

•

PLL enable fields—The PMMPLLnCTL1.PLLEN fields enable the corresponding PLLs to run.

16.6 Switching Between Power Modes

Switching from a higher to a lower power consumption mode is performed by writing an appropriate value

to the Power Management Control Register (PMMSTCTL). Switching from a lower power consumption

mode to the Active mode is usually triggered by a hardware event. Figure 16-1 shows the four power

modes and the events that trigger a transition from one mode to another.

Power Management Module

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