CP3SP33SMSSLASHNOPB datasheet(9/407 Pages) TI1

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CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

3.9

Audio/Telematics Codec

The on-chip codec is designed for voice input and stereo audio playback. It includes dual mono ADC

channels operating at a sample rate of 8–24 kHz (125× oversampling clock required). A stereo DAC

operates at selected sample rates from a 125× or 128× oversampling clock, driving two configurable, gain-

programmable differential line driver outputs. The DAC features click and pop reduction, zero-crossing

detection, tone/compensation filter, sidetone injection from the ADC, and internal power management. The

ADCs accept differential or single-ended analog microphone inputs. The DAC employs fully differential

signaling for high PSRR and low crosstalk. DMA transfers are supported to allow for fast CPU-

independent receive and transmit.

3.10 CVSD/PCM Conversion Modules

The two CVSD/PCM modules perform conversion between CVSD data and PCM data, in which the CVSD

encoding is as defined in the Bluetooth specification and the PCM data can be 8-bit µ-Law, 8-bit A-Law, or

13-bit to 16-bit Linear.

3.11 I

2S Digital Audio Bus

The Inter-IC Sound (I2S) interface is a synchronous serial interface intended for the transfer of digital

audio data. The I2S interface can be configured as a master or a slave, and it supports all three common

data formats: I2S-mode, left-justified, and right-justified. It has programmable word length from 8 to 32 bits

and programmable valid data resolution from 8 to 24 bits.

3.12 Advanced Audio Interface

The Advanced Audio Interface (AAI) provides a serial synchronous, full-duplex interface to codecs and

similar serial devices. Transmit and receive paths operate asynchronously with respect to each other.

Each path uses three signals for communication: shift clock, frame synchronization, and data.

When the receiver and transmitter use external shift clocks and frame sync signals, the interface operates

in its asynchronous mode. Alternatively, the transmit and receive path can share the same shift clock and

frame sync signals for synchronous mode operation.

3.13 Analog to Digital Converter

This device contains a 10-channel, multiplexed input, successive approximation, 10-bit Analog-to-Digital

Converter. It supports both single-ended and differential modes of operation.

The integrated 10-bit ADC provides the following features:

•

10-channel, multiplexed input

•

5 differential channels

•

Single-ended and differential external filtering capability

•

12-bit resolution; 10-bit accuracy

•

Sign bit

•

10-microsecond conversion time

•

External start trigger

•

Programmable start delay after start trigger

•

Poll or interrupt on conversion completion

The ADC provides several options for the voltage reference source. The positive reference can be

ADVCC (internal), VREF, ADC0, or ADC1. The negative reference can be AD-VCC (internal), ADC2, or

ADC3.

Two specific analog channel selection modes are supported. These are as follows:

•

Allow any specific channel to be selected at one time. The A/D Converter performs the specific

conversion requested and stops.

Device Overview

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