CP3SP33SMSSLASHNOPB datasheet(55/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

RFCKEN

The RF Clock Enable bit controls whether Main Clock is driven on the CLKIN/RFCK

pin.

0 – Main Clock is not driven on CLKIN/RFCK.

1 – Main Clock is driven on CLKIN/RFCK.

BTHCLKDIS

The Bluetooth Clock Disable bit controls whether HCLK Clock to the Bluetooth

module is disabled.

0 – HCLK Clock is available to the Bluetooth module.

1 – HCLK Clock is not available to the Bluetooth module.

USBHCLKDIS

The USB Clock Disable bit controls whether the HCLK Clock to the USB module is

disabled.

0 – HCLK Clock is available to the USB module.

1 – HCLK Clock is not available to the USB module.

USBIDDIGPUEN

The USB IDDIG Pullup Enable bit controls whether the USB module can enable the

internal pullup on the PE15 port pin. This mode only applies when the IDDIG

alternate function for PE15 is enabled.

0 – Internal pullup on PE15 is disabled when IDDIG alternate function is selected.

1 – USB module controls internal pullup on PE15 when IDDIG alternate function is

selected.

XDPUDIS

The XD Pullup Disable bit controls whether weak pullup resistors are enabled on the

XD external data bus.

0 – Weak pullups on XD bus.

1 – No pullups on XD bus.

12 CPU DMA Controller

The CPU DMA controller (DMAC) can be used to accelerate peripheral-to-memory, memory-to-peripheral,

and memory-to-memory block transfers. Because it uses cycle stealing to interleave bus cycles with the

CPU, DMA-based data movement uses the available bandwidth on the CPU core bus more efficiently than

software-based data movement

The DMAC provides 16 DMA channels, which may be assigned to any of 34 peripheral registers. For

registers that are loaded by the peripheral (such as a UART receive register), the DMAC gets a DMA

request when the register is loaded. It then reads the register and writes the data to memory. For registers

that are unloaded by the peripheral (such as a UART transmit register), the DMAC gets a DMA request

when the register is empty. It then reads data from memory and writes the data to the register. Only one

DMA may be used for software DMA (memory-to-memory block transfers).

The DMAC has a register-based programming interface (as opposed to I/O control blocks). After loading

the registers with source and destination addresses, as well as block size and type of operation, a DMAC

channel is ready to respond to DMA transfer requests. A request can only come from onchip peripherals

or software, not external peripherals. On receiving a DMA transfer request, if the channel is enabled, the

DMAC performs the following operations:

1. Arbitrates to become master of the CPU core bus.

2. Determines priority among the DMAC requests. Priority is linear, with channel 0 having the highest

priority.

3. Executes data transfer bus cycle(s) specified by the programming of the control registers for the

channel being serviced. This may be a single cycle or a four cycle burst.

4. If the DMA transfer cycle is complete, the DMAC does the following:

–

Updates the termination bits.

–

Asserts an interrupt (if enabled).

5. Returns control of the CPU core bus to the CPU, even if a DMA request continues to be asserted.

Priority among DMA channels is re-determined after every cycle.

CPU DMA Controller

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