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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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VSC8504-02 датащи(PDF) 119 Page - Microsemi Corporation |
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VSC8504-02 датащи(HTML) 119 Page - Microsemi Corporation |
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119 / 131 page  Pin Descriptions VMDS-10507 VSC8504-02 Datasheet Revision 4.2 108 6.3.1 GPIO and SIGDET The following table lists the GPIO and SIGDET pins. 6.3.2 JTAG The following table lists the JTAG test pins. 6.3.3 Miscellaneous The following table lists the miscellaneous pins. Table 127 • GPIO and SIGDET Pins Name Pin Type Description GPIO0/SIGDET0 GPIO1/SIGDET1 GPIO2/SIGDET2 GPIO3/SIGDET3 GPIO4/I2C_SCL_0 GPIO5/I2C_SCL_1 GPIO6/I2C_SCL_2 GPIO7/I2C_SCL_3 GPIO8/I2C_SDA GPIO9/FASTLINK-FAIL GPIO10 GPIO11 GPIO12 GPIO13 N14 M14 M15 M16 L13 L14 L15 L16 K13 K14 K15 K16 J14 H14 I/O, PU, 3 V General purpose input/output (GPIO). The multipurpose SIGDET pins, two-wire serial controller pins, and fast link fail pin can be configured to serve as GPIOs. Table 128 • JTAG Pins Name Pin Type Description TCK F3 I, PU, ST, 3 V JTAG test clock input. TDI F2 I, PU, ST, 3 V JTAG test serial data input. TDO F1 O JTAG test serial data output. TMS E2 I, PU, ST, 3 V JTAG test mode select. TRST E3 I, PU, ST, 3 V JTAG reset. Important When JTAG is not in use, this pin must be tied to ground with a pull-down resistor for normal operation. Table 129 • Miscellaneous Pins Name Pin Type Description CLK_SQUELCH_IN E15 I, PU, 3V Input control to squelch recovered clock. COMA_MODE L3 I, PU, 3V When this pin is asserted high, all PHYs are held in a powered down state. When de-asserted low, all PHYs are powered up and resume normal operation. This signal is also used to synchronize the operation of multiple chips on the same PCB to provide visual synchronization for LEDs driven by separate chips.(1) |
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