VSC8504-02 datasheet(34/131 Pages) MICROSEMI

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Functional Descriptions

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

3.11.2

Clock Output Squelch

Under certain conditions, the PHY outputs a clock based on the REFCLK_P and REFCLK_N pins, such

as when there is no link present or during autonegotiation. To prevent an undesirable clock from

appearing on the recovered clock pins, the VSC8504-02 squelches, or inhibits, the clock output based on

any of the following criteria:

•

No link is detected (the link status register 1, bit 2 = 0). In fiber media modes, sync status is required

to unsquelch the recovered clock output instead of link status.

•

The link is found to be unstable using the fast link failure detection feature. The

GPIO9/FASTLINK-FAIL pin is asserted high when enabled.

•

The active link is in 10BASE-T or in 1000BASE-T master mode. These modes produce unreliable

recovered clock sources.

•

CLK_SQUELCH_IN is enabled to squelch the clock.

Use registers 23G or 24G, bits 5:4 to configure the clock squelch criteria. These registers can also

disable the squelch feature. The CLK_SQUELCH_IN pin controls the squelching of the clock. Both

RCVRDCLK1 and RCVRDCLK2 are squelched when the CLK_SQUELCH_IN pin is high.

3.12

Serial Management Interface

The VSC8504-02 device includes an IEEE 802.3-compliant serial management interface (SMI) that is

affected by use of its MDC and MDIO pins. The SMI provides access to device control and status

registers. The register set that controls the SMI consists of 32 16-bit registers, including all required

IEEE-specified registers. Also, there are additional pages of registers accessible using device register

31.

Energy efficient Ethernet control registers are available through the SMI using Clause 45 registers and

Clause 22 register access in registers 13 through 14. For more information, see Table 7, page 26 and

Table 68, page 74.

The SMI is a synchronous serial interface with input data to the VSC8504-02 on the MDIO pin that is

clocked on the rising edge of the MDC pin. The output data is sent on the MDIO pin on the rising edge of

the MDC signal. The interface can be clocked at a rate from 0 MHz to 12.5 MHz, depending on the total

load on MDIO. An external 2-k

Ω pull-up resistor is required on the MDIO pin.

3.12.1

SMI Frames

Data is transferred over the SMI using 32-bit frames with an optional, arbitrary-length preamble. Before

the first frame can be sent, at least two clock pulses on MDC must be provided with the MDIO signal at

logic one to initialize the SMI state machine. The following illustrations show the SMI frame format for

read and write operations.

Figure 26 •

SMI Read Frame

MDIO

Idle Preamble

(optional)

SFD

Read

MDC

Station manager drives MDIO

PHY drives MDIO

PHY Address

to PHY

from PHY

Idle

A4 A3 A2 A1 A0 R4 R3 R2 R1 R0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2

D0 Z

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