VSC8504-02 datasheet(40/131 Pages) MICROSEMI

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Functional Descriptions

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

3.13.5

Enhanced Serial LED Mode

VSC8504-02 can be configured to output up to four LED signals per port on a serial stream that can be

de-serialized externally to drive LEDs on the system board. In enhanced serial LED mode, the port 0 and

port 1 LED output pins serve the following functions:

•

LED0_0/LED0_1: LED_DATA

•

LED1_0/LED1_1: LED_CLK

•

LED2_0/LED2_1: LED_LD

•

LED3_0/LED3_1: LED_PULSE

The serial LED_DATA is shifted out on the falling edge of LED_CLK and is latched in the external

serial-to-parallel converter on the rising edge of LED_CLK. The falling edge of LED_LD signal can be

used to shift the data from the shift register in the converter to the parallel output drive register. When a

separate parallel output drive register is not used in the external serial-to-parallel converter, the LEDs will

blink at a high frequency as the data bits are being shifted through, which may be undesirable. LED pin

functionality is controlled by setting register 25G, bits 7:1.

The LED_PULSE signal provides a 5 kHz pulse stream whose duty cycle can be modulated to turn on/off

LEDs at a high rate. This signal can be tied to the output enable signal of the serial-to-parallel converter

to provide the LED dimming functionality to save energy. The LED_PULSE duty cycle is controlled by

setting register 25G, bits 15:8.

3.13.6

LED Port Swapping

For additional hardware configurations, the VSC8504-02 can have its LED port order swapped. This is a

useful feature to help simplify PCB layout design. Register 25G bit 0 controls the LED port swapping

mode.

Note: LED port swapping only applies to the parallel LED outputs and does not affect the serial LED outputs.

3.14

Fast Link Failure Indication

To aid Synchronous Ethernet applications, the VSC8504-02 can indicate the onset of a link failure in less

than 1 ms (worst-case <3 ms). By comparison, the IEEE 802.3 standard establishes a delay of up to

750 ms before indicating that a 1000BASE-T link is no longer present. A fast link failure indication is

critical to support ports used in a synchronization timing link application. The fast link failure indication

works for all copper media speeds, but not for fiber media. Fast link failure is supported for each PHY

port through the GPIO9/FASTLINK-FAIL pin. For details on how to use the FASTLINK-FAIL pin, see

Table 50, page 63 and Table 81, page 81.

Note: For all links except 1000BASE-T, the fast link failure indication matches the link status register (address

1, bit 2). For 1000BASE-T links, the link failure is based on a circuit that analyzes the integrity of the link,

and at the indication of failure, will assert.

Note: The Fast Link Failure Indication should not be used when EEE is enabled on a link.

3.15

Integrated Two-Wire Serial Multiplexer

The VSC8504-02 includes an integrated quad two-wire serial multiplexer (MUX), eliminating the need for

an external two-wire serial device for the control and status of SFP or PoE modules. There are five

two-wire serial controller pins: four clocks and one shared data pin. Each SFP or PoE connects to the

Activity

Fiber activity

Tx activity

10223446

Rx activity

Autonegotiation fault

Table 9 •

LED Serial Bitstream Order (continued)

Output

PHY0 PHY1 PHY2 PHY3

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