VSC8504-02 datasheet(48/131 Pages) MICROSEMI

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Functional Descriptions

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

tmp17 = PhyRead(<phy>,17);

if (set)

tmp17 |= 0x0010; //Set SigDet as desired, Set bit 4

else // clear SigDet

tmp17 &= 0xffef; //Clear SigDet, bit 4

PhyWrite(<phy>, 17, tmp17);

PhyWrite(<phy>, 16, 0x868a);

PhyWrite(<phy>, 31, 0x0);

3.17.6.6 Input Loop

The received 1-bit data stream of the input buffer is looped back asynchronously to the output buffer. This

test loop provides the possibility to test only the analog parts of the SGMII interface because only the

input and output buffer are part of this loop.

Note: When the enhanced SerDes macro is in input loopback, the output is inverted relative to the input.

The following table shows the SerDes macro address map.

3.17.7

VeriPHY Cable Diagnostics

The VSC8504-02 includes a comprehensive suite of cable diagnostic functions that are available using

SMI reads and writes. These functions enable a variety of cable operating conditions and status to be

accessed and checked. The VeriPHY suite has the ability to identify the cable length and operating

conditions and to isolate a variety of common faults that can occur on Cat5 twisted pair cabling.

For functional details of the VeriPHY suite and the operating instructions, see the ENT-AN0125 PHY,

Integrated PHY-Switch VeriPHY - Cable Diagnostics application note.

3.17.8

JTAG Boundary Scan

The VSC8504-02 supports the test access port (TAP) and boundary scan architecture described in

IEEE 1149.1. The device includes an IEEE 1149.1-compliant test interface, referred to as a JTAG TAP

interface.

The JTAG boundary scan logic on the VSC8504-02, accessed using its TAP interface, consists of a

boundary scan register and other logic control blocks. The TAP controller includes all IEEE-required

signals (TMS, TCK, TDI, and TDO), in addition to the optional asynchronous reset signal TRST. The

following illustration shows the TAP and boundary scan architecture.

Important When JTAG is not in use, the TRST pin must be tied to ground with a pull-down resistor for

normal operation.

Table 11 •

SerDes Macro Address Map

SerDes Macro

Physical Address (s)

Interface Logical Type (p)

Address

SerDes0

0x0

Fiber0

0x1

SerDes1

0x1

SGMII1

0x1

SerDes2

0x2

Fiber1

0x2

SerDes3

0x3

SGMII2

0x2

SerDes4

0x4

Fiber2

0x4

SerDes5

0x5

SGMII3

0x3

SerDes6

0x6

Fiber3

0x8

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