VSC8504-02 datasheet(94/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

4.6.13

Recovered Clock 2 Control

signal.

10:8

Clock frequency

select

R/W

Select output clock frequency:

000: 25 MHz output clock

001: 125 MHz output clock

010: 31.25 MHz output clock

011–111: Reserved

000

7:6

Reserved

Reserved.

5:4

Clock squelch level R/W

Select clock squelch level

00: Automatically squelch clock to low when the

link is not up, is unstable, is up in a mode that

does not support the generation of a recovered

clock (1000BASE-T master or 10BASE-T), or is

up in EEE mode (100BASE-TX or 1000BASE-T

slave).

01: Same as 00 except that the clock is also

generated in 1000BASE-T master and 10BASE-T

link-up modes. This mode also generates a

recovered clock output in EEE mode during

reception of LP_IDLE.

10: Squelch only when the link is not up.

11: Disable clock squelch.

Note: A clock from the SerDes or Cu PHY

will be output on the recovered

clock output in this mode when the

link is down.

When the CLK_SQUELCH_IN pin is set high, it

squelches the recovered clocks regardless of bit

settings.

Reserved

Reserved.

2:0

Clock selection for

specified PHY

R/W

000: Serial media recovered clock

001: Copper PHY recovered clock

010: Copper PHY transmitter TCLK

011–111: Reserved

000

Table 86 •

Recovered Clock 2 Control, Address 24G (0x18)

Bit

Name

Access Description

Default

Enable RCVRDCLK2 R/W

Enable recovered clock 2 output

14:11

Clock source select

R/W

Select bits for source PHY for recovered clock:

0000: PHY0

0001: PHY1

0010: PHY2

0011: PHY3

0100–1111: Reserved

0000

Table 85 •

Recovered Clock 1 Control, Address 23G (0x17) (continued)

Bit

Name

Access Description

Default

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