VSC8504-02 datasheet(80/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

4.4.3

Ring Resiliency Control

The following table shows the register settings for the ring resiliency controls at address 30E2.

Enable LED in fiber

unidirectional mode

R/W

Sticky bit.

1: Enable LED functions in fiber unidirectional

mode.

13:10 Invert LED polarity

R/W

Sticky bits.

Invert polarity of LED[3:0]_[3:0] signals. Default

is to drive an active low signal on the LED pins.

This also applies to enhanced serial LED mode.

For more information, see Enhanced Serial LED

Mode, page 29.

0000

9:6

Reserved

Reserved.

Enable 1000BASE-T

force mode

R/W

Sticky bit.

1: Enable 1000BASE-T force mode to allow PHY

to link-up in 1000BASE-T mode without forcing

master/slave when register 0, bits 6 and 13 are

set to 2’b10.

Force transmit LPI

R/W

Sticky bit.

1: Enable the EPG to transmit LPI on the MDI,

ignore data from the MAC interface.

0: Transmit idles being received from the MAC.

Inhibit 100BASE-TX

transmit EEE LPI

R/W

Sticky bit.

1: Disable transmission of EEE LPI on transmit

path MDI in 100BASE-TX mode when receiving

LPI from MAC.

Inhibit 100BASE-TX

receive EEE LPI

R/W

Sticky bit.

1: Disable transmission of EEE LPI on receive

path MAC interface in 100BASE-TX mode when

receiving LPI from the MDI.

Inhibit 1000BASE-T

transmit EEE LPI

R/W

Sticky bit.

1: Disable transmission of EEE LPI on transmit

path MDI in 1000BASE-T mode when receiving

LPI from MAC.

Inhibit 1000BASE-T

receive EEE LPI

R/W

Sticky bit.

1: Disable transmission of EEE LPI on receive

path MAC interface in 1000BASE-T mode when

receiving LPI from the MDI.

17E2 bits 4:0 are for debugging purposes only, not for operational use.

Table 58 •

Ring Resiliency, Address 30E2

Bit

Name

Access Description

Default

Ring resiliency

startup enable

(master TR enable)

R/W

Sticky

Advertise ring

resiliency

R/W

Sticky

Table 57 •

EEE Control, Address 17E2 (0x11) (continued)

Bit

Name

Access Description

Default

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