VSC8504-02 datasheet(43/131 Pages) MICROSEMI

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Functional Descriptions

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

3.17

Testing Features

The VSC8504-02 device includes several testing features designed to facilitate performing system-level

debugging and in-system production testing. This section describes the available features.

3.17.1

Ethernet Packet Generator

The Ethernet packet generator (EPG) can be used at each of the 10/100/1000BASE-T speed settings for

copper Cat5 media and fiber media to isolate problems between the MAC and the VSC8504-02, or

between a locally connected PHY and its remote link partner. Enabling the EPG feature effectively

disables all MAC interface transmit pins and selects the EPG as the source for all data transmitted onto

the twisted pair interface. This feature is not used when the SerDes media is set to pass-through mode.

Important The EPG is intended for use with laboratory or in-system testing equipment only. Do not use

the EPG testing feature when the VSC8504-02 is connected to a live network.

To enable the VSC8504-02 EPG feature, set the device register bit 29E1.15 to 1.

When the EPG is enabled, packet loss occurs during transmission of packets from the MAC to the PHY.

However, the PHY receive output pins to the MAC are still active when the EPG is enabled. When it is

necessary to disable the MAC receive pins as well, set the register bit 0.10 to 1.

When the device register bit 29E1.14 is set to 1, the PHY begins transmitting Ethernet packets based on

the settings in registers 29E1 and 30E1. These registers set:

•

Source and destination addresses for each packet

•

Packet size

•

Interpacket gap

•

FCS state

•

Transmit duration

•

Payload pattern

When register bit 29E1.13 is set to 0, register bit 29E1.14 is cleared automatically after 30,000,000

packets are transmitted.

3.17.2

CRC Counters

Two sets of cyclical redundancy check (CRC) counters are available in all PHYs in VSC8504-02. One set

monitors traffic on the copper interface and the other set monitors traffic on the SerDes interface.

The device CRC counters operate in the 100BASE-FX/1000BASE-X over SerDes mode as well as in the

10/100/1000BASE-T mode as follows:

After receiving a packet on the media interface, register bit 15 in register 18E1 or register 28E3 is set and

cleared after being read.

The packet then is counted by either the good CRC counter or the bad CRC counter.

Both CRC counters are also automatically cleared when read.

The good CRC counter’s highest value is 9,999 packets. After this value is reached, the counter clears

on the 10,000th packet and continues to count additional packets beyond that value. The bad CRC

counter stops counting when it reaches its maximum counter limit of 255 packets.

GPIO4/I2C_SCL_0

13G.9:8.

15G.4

16G.4

17G.4

GPIO5/I2C_SCL_1

13G.11:10

15G.5

16G.5

17G.5

GPIO6/I2C_SCL_2

13G.13:12

15G.6

16G.6

17G.6

GPIO7/I2C_SCL_3

13G.15:14

15G.7

16G.7

17G.7

GPIO8/I2C_SDA

14G.1:0

15G.8

16G.8

17G.8

GPIO9/FASTLINK_FAIL

14G.3:2

15G.9

16G.9

17G.9

Table 10 •

GPIO Pin

GPIO_ctrl

GPIO Input

GPIO Output

GPIO Output Enable

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