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VSC8504-02 датащи(PDF) 52 Page - Microsemi Corporation |
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VSC8504-02 датащи(HTML) 52 Page - Microsemi Corporation |
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52 / 131 page ![]() Functional Descriptions VMDS-10507 VSC8504-02 Datasheet Revision 4.2 41 PhyWrite(<phy>, 18, reg18); PhyWrite(<phy>, 17, reg17); PhyWrite(<phy>, 16, 0x9e80); Sweeping through all five pattern shifts checking for a match: for (i = 0, matchfailed = 1; i < 5 && matchfailed; ++i) { PhyWrite(<phy>, 16, 0xac84); reg18 = PhyRead(<phy>, 18); reg18 = (reg18 & 0xf0) | (patternset[i] >> 16) PhyWrite(<phy>, 18, reg18); PhyWrite(<phy>, 17, patternset[i] & 0xffff); PhyWrite(<phy>, 16, 0x8c84); PhyWrite(<phy>, 16, 0xbe84); // Dummy read to clear latched mismatch PhyWrite(<phy>, 16, 0xbe84); // Read pattern check failure status matchfailed = PhyRead(<phy>, 17) & 1; // Extract pattern check failure status } Turning off the pattern checker: PhyWrite(<phy>, 16, 0xbe80); reg18 = PhyRead(<phy>, 18); reg17 = PhyRead(<phy>, 17); reg17 = reg17 & ~4; PhyWrite(<phy>, 18, reg18); PhyWrite(<phy>, 17, reg17); PhyWrite(<phy>, 16, 0x9e80); PhyWrite(<phy>, 31, 0); HALT_codeword_detected =!matchfailed; 3.19 Configuration The VSC8504-02 can be configured by setting internal memory registers using the management interface. To configure the device, perform the following steps: 1. COMA_MODE active, drive high (optional). 2. Apply power. 3. Apply RefClk. 4. Release reset, drive high. Power and clock must be stable before releasing reset. 5. Wait 120 ms minimum. 6. Apply patch from PHY_API (required for production released optional for board testing). 7. Configure register 19G for MAC mode (to access register 19G, register 31 must be 0x10). Read register 19G. Set bits 15:14, MAC configuration as follows: 00: SGMII 01: QSGMII 10: Reserved 11: Reserved Write new register 19G. 8. Configure register 18G for MAC on all 4 PHYs write: SGMII: 0x80F0 QSGMII: 0x80E0 Read register 18G until bit 15 equals 0. 9. If Fiber Media on all 4 PHYs configure register 18G by writing: Media 1000BASE-X: 0x8FC1 Media 100BASE-FX: 0x8FD1 10. If Fiber Media read register 18G till bit 15 equals 0. 11. Configure register 23 for MAC and Media mode (to access register 23, register 31 must be 0). Read register 23. Set bits 10:8 as follows: 000: Copper |
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