VSC8504-02 datasheet(35/131 Pages) MICROSEMI

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Functional Descriptions

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

Figure 27 •

SMI Write Frame

The following list provides additional information about the terms used in the SMI read and write timing

diagrams.

•

Idle—During idle, the MDIO node goes to a high-impedance state. This allows an external pull-up

resistor to pull the MDIO node up to a logical 1 state. Because the idle mode does not contain any

transitions on MDIO, the number of bits is undefined during idle.

•

Preamble—By default, preambles are not expected or required. The preamble is a string of ones. If

it exists, the preamble must be at least 1 bit; otherwise, it can be of an arbitrary length.

•

Start of Frame (SFD)—A pattern of 01 indicates the start of frame. If the pattern is not 01, all

following bits are ignored until the next preamble pattern is detected.

•

Read or Write Opcode—A pattern of 10 indicates a read. A 01 pattern indicates a write. If the bits are

not either 01 or 10, all following bits are ignored until the next preamble pattern is detected.

•

PHY Address—The particular VSC8504-02 responds to a message frame only when the received

PHY address matches its physical address. The physical address is 5 bits long (4:0).

•

Turnaround—The two bits used to avoid signal contention when a read operation is performed on

the MDIO are called the turnaround (TA) bits. During read operations, the VSC8504-02 drives the

second TA bit, a logical 0.

•

Data—The 16-bits read from or written to the device are considered the data or data stream. When

data is read from a PHY, it is valid at the output from one rising edge of MDC to the next rising edge

of MDC. When data is written to the PHY, it must be valid around the rising edge of MDC.

•

Idle—The sequence is repeated.

3.12.2

SMI Interrupt

The SMI includes an output interrupt signal, MDINT, for signaling the station manager when certain

events occur in the VSC8504-02.

The MDINT pin can be configured for open-drain (active-low) by tying the pin to a pull-up resistor and to

VDDIO. The following illustration shows this configuration.

Figure 28 •

MDINT Configured as an Open-Drain (Active-Low) Pin

Alternatively, the MDINT pin can be configured for open-source (active-high) by tying the pin to a pull-

down resistor and to VSS. The following illustration shows this configuration.

MDIO

Idle Preamble

(optional)

SFD

Write

MDC

Station manager drives MDIO (PHY tri-states MDIO during the entire sequence)

PHY Address

to PHY

from PHY

Idle

A4 A3 A2 A1 A0 R4 R3 R2 R1 R0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2

D0 Z

MDINT

(to the Station

Manager)

Interrupt Pin Enable

(Register 25.15)

Interrupt Pin Status

(Register 26.15)

External Pull-up

Resistor at the

Station Manager

for Open-drain

(Active-low Mode)

VDDIO

PHY_n

MDINT

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