VSC8504-02 datasheet(76/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

4.3.5

PoE and Miscellaneous Functionality

The register at address 23E1 controls various aspects of inline powering and the CRC error counter in

the VSC8504-02.

RC error counter for packets received on the Cu media interface. The value saturates at 0xFF and

subsequently clears when read and restarts count.0x00

4.3.6

Ethernet Packet Generator Control 1

The EPG control register provides access to and control of various aspects of the EPG testing feature.

There are two separate EPG control registers. The following table shows the settings available in the first

Reserved

Table 52 •

Extended PHY Control 4, Address 23E1 (0x17)

Bit

Name

Access Description

Default

15:11

PHY address

PHY address; latched on reset

Inline powered device

detection

R/W

Sticky bit.

1: Enabled

9:8

Inline powered device

detection status

Only valid when bit 10 is set.

00: Searching for devices

01: Device found; requires inline power

10: Device found; does not require inline

power

11: Reserved

7:0

Cu Media CRC error

counter

Self-clearing bit

Table 53 •

EPG Control Register 1, Address 29E1 (0x1D)

Bit

Name

Access Description

Default

EPG enable

R/W

1: Enable EPG

EPG run or stop

R/W

1: Run EPG

Transmission duration R/W

1: Continuous (sends in 10,000-packet

increments)

0: Send 30,000,000 packets and stop

12:11

Packet length

R/W

00: 125 bytes

01: 64 bytes

10: 1518 bytes

11: 10,000 bytes (jumbo packet)

Interpacket gap

R/W

1: 8,192 ns

0: 96 ns

9:6

Destination address

R/W

Lowest nibble of the 6-byte destination

address

0001

5:2

Source address

R/W

Lowest nibble of the 6-byte destination

address

0000

Table 51 •

Extended PHY Control 3, Address 20E1 (0x14) (continued)

Bit

Name

Access Description

Default

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