VSC8504-02 datasheet(65/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

4.2.17

Error Counter 1

The bits in register 19 provide an error counter. The following table shows the settings available.

4.2.18

Error Counter 2

The bits in register 20 provide an error counter. The following table shows the settings available.

4.2.19

Error Counter 3

The bits in register 21 provide an error counter. The following table shows the settings available.

4.2.20

Extended Control and Status

The bits in register 22 provide additional device control and readouts. The following table shows the

settings available.

Table 35 •

Error Counter 1, Address 19 (0x13)

Bit

Name

Access Description

Default

15:8 Reserved

Reserved.

7:0

100/1000 receive

error counter

8-bit counter that saturates when it reaches

255. These bits are self-clearing when read.

0x00

Table 36 •

Error Counter 2, Address 20 (0x14)

Bit

Name

Access Description

Default

15:8 Reserved

Reserved.

7:0

100/1000 false carrier

counter

8-bit counter that saturates when it reaches

255. These bits are self-clearing when read.

0x00

Table 37 •

Error Counter 3, Address 21 (0x15)

Bit

Name

Access Description

Default

15:8 Reserved

Reserved.

7:0

Copper media link

disconnect counter

8-bit counter that saturates when it reaches

255. These bits are self-clearing when read.

0x00

Table 38 •

Extended Control and Status, Address 22 (0x16)

Bit

Name

Access Description

Default

Force 10BASE-T link high

R/W

Sticky bit.

1: Bypass link integrity test

0: Enable link integrity test

Jabber detect disable

R/W

Sticky bit.

1: Disable jabber detect

Disable 10BASE-T echo

R/W

Sticky bit.

1: Disable 10BASE-T echo

Disable SQE mode

R/W

Sticky bit.

1: Disable SQE mode

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