VSC8504-02 datasheet(36/131 Pages) MICROSEMI

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Functional Descriptions

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

Figure 29 •

MDINT Configured as an Open-Source (Active-High) Pin

When a PHY generates an interrupt, the MDINT pin is asserted (driven high or low, depending on resistor

connection) if the interrupt pin enable bit (MII register 25.15) is set.

3.13

LED Interface

The LED interface supports the following configurations: direct drive, basic serial LED mode, and

enhanced serial LED mode. The polarity of the LED outputs is programmable and can be changed

through register 17E2, bits 13:10. The default polarity is active low.

Direct drive mode provides four LED signals per port, LED0_[0:3] through LED3_[0:3]. The mode and

function of each LED signal can be configured independently. When serial LED mode is enabled, the

direct drive pins not used by the serial LED interface remain available.

In basic serial LED mode, all signals that can be displayed on LEDs are sent as LED_Data and

LED_CLK for external processing. In enhanced serial LED mode, up to four LED signals per port can be

sent as LED_Data, LED_CLK, LED_LD, and LED_Pulse. The following sections provide detailed

information about the various LED modes.

Note: LED number is listed using the convention, LED<LED#>_<Port#>.

The following table shows the bit 9 settings for register 14G that are used to control the LED behavior for

all the LEDs in VSC8504-02.

Note: Enhanced serial LED mode will use the VDD LED drive state (alternate setting), regardless of the setting

in register 14G.9.

3.13.1

LED Modes

Each LED pin can be configured to display different status information that can be selected by setting the

LED mode in register 29. The modes listed in the following table are equivalent to the setting used in

modifying the value in register 17E2, bits 13:10. The blink/pulse-stretch is dependent on the LED

behavior setting in register 30.

Table 6 •

LED Drive State

Setting

Active

Not Active

14G.9 = 1 (default)

Ground

Tristate

14G.9 = 0 (alternate setting)

Ground

VDD

MDINT

(to the Station

Manager)

Interrupt Pin Enable

(Register 25.15)

Interrupt Pin Status

(Register 26.15)

External Pull-down

at the Station

Manager

For Open-source

(Active-high Mode)

VDDIO

PHY_n

MDINT

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