VSC8504-02 datasheet(58/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

4.2.3

Device Identification

All 16 bits in both register 2 and register 3 in the VSC8504-02 are used to provide information associated

with aspects of the device identification. The following tables list the expected readouts.

4.2.4

Autonegotiation Advertisement

The bits in address 4 in the main registers space control the VSC8504-02 ability to notify other devices of

the status of its autonegotiation feature. The following table shows the available settings and readouts.

Autonegotiation complete

1: Autonegotiation complete.

Remote fault

Latches high.

1: Far-end fault detected.

Autonegotiation capability

1: Autonegotiation capable.

Link status

Latches low.

1: Link is up.

Jabber detect

Latches high.

1: Jabber condition detected.

Extended capability

1: Extended register capable.

Table 20 •

Identifier 1, Address 2 (0x02)

Bit

Name

Access Description

Default

15:0 Organizationally unique identifier

(OUI)

OUI most significant bits (3:18)

0×0007

Table 21 •

Identifier 2, Address 3 (0x03)

Bit

Name

Access Description

Default

15:10 OUI

OUI least significant bits (19:24)

000001

9:4

Microsemi model

number

VSC8504-02 (0xC)

001100

3:0

Device revision number RO

See register 30G for the extended

revision identification of this

device.

0010

Table 22 •

Device Autonegotiation Advertisement, Address 4 (0x04)

Bit Name

Access Description

Default

Next page transmission request R/W

1: Request enabled

Reserved

Transmit remote fault

R/W

1: Enabled

Reserved

R/W

Reserved

Advertise asymmetric pause

R/W

1: Advertises asymmetric pause

Advertise symmetric pause

R/W

1: Advertises symmetric pause

Advertise100BASE-T4

R/W

1: Advertises 100BASE-T4

Advertise100BASE-TX FDX

R/W

1: Advertise 100BASE-TX FDX

Table 19 •

Mode Status, Address 1 (0x01) (continued)

Bit Name

Access Description

Default

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