VSC8504-02 datasheet(91/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

4.6.6

GPIO Pin Configuration

an output. The following table shows the settings available.

4.6.7

Microprocessor Command

bit 15 is cleared the command has completed. Software needs to wait until bit 15 = 0 before proceeding

with the next PHY register access. Bit 14 = 1 typically indicates an error condition where the squelch

patch was not loaded. Use the following steps to execute the command:

Write desired command

Check bit 15 (move existing text)

Check bit 14 (if set, then error)

Note: Commands may take up to 25 ms to complete before bit 15 changes to 0.

GPIO0/SIGDET0

R/W

GPIO0/SIGDET0 output

Table 79 •

GPIO Input/Output Configuration, Address 17G (0x11)

Bit

Name

Access Description

Default

15:14

Reserved

GPIO13

R/W

GPIO13 output enable

GPIO12

R/W

GPIO12 output enable

GPIO11

R/W

GPIO11 output enable

GPIO10

R/W

GPIO10 output enable

GPIO9/FASTLINK_FAIL

R/W

GPIO9/FASTLINK_FAIL output enable 0

GPIO8/I2C_SDA

R/W

GPIO8/I2C_SDA output enable

GPIO7/I2C_SCL_3

R/W

GPIO7/I2C_SCL_3 output enable

GPIO6/I2C_SCL_2

R/W

GPIO6/I2C_SCL_2 output enable

GPIO5/I2C_SCL_1

R/W

GPIO5/I2C_SCL_1 output enable

GPIO4/I2C_SCL_0

R/W

GPIO4/I2C_SCL_0 output enable

GPIO3/SIGDET3

R/W

GPIO3/SIGDET3 output enable

GPIO2/SIGDET2

R/W

GPIO2/SIGDET2 output enable

GPIO1/SIGDET1

R/W

GPIO1/SIGDET1 output enable

GPIO0/SIGDET0

R/W

GPIO0/SIGDET0 output

Table 80 •

Microprocessor Command Register, Address 18G

Command

Setting

Enable 4 ports MAC SGMII

0x80F0

Enable 4 ports MAC QSGMII

0x80E0

QSGMII transmitter control(1)

Enable 4 ports Media 1000BASE-X

0x8FC1(2)

Enable 4 ports Media 100BASE-FX

0x8FD1(2)

Table 78 •

GPIO Output, Address 16G (0x10) (continued)

Bit

Name

Access Description

Default

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