VSC8504-02 datasheet(98/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

4.7.2

EEE Capability

This register is used to indicate the capability of the PCS to support EEE functions for each PHY type.

The following table shows the bit assignments for the EEE capability register.

4.7.3

EEE Wake Error Counter

This register is used by PHY types that support EEE to count wake time faults where the PHY fails to

complete its normal wake sequence within the time required for the specific PHY type. The definition of

the fault event to be counted is defined for each PHY and can occur during a refresh or a wakeup as

defined by the PHY. This 16-bit counter is reset to all zeros when the EEE wake error counter is read or

when the PHY undergoes hardware or software reset.

4.7.4

EEE Advertisement

This register defines the EEE advertisement that is sent in the unformatted next page following a EEE

technology message code. The following table shows the bit assignments for the EEE advertisement

Tx LPI indication

1: Tx PCS is currently receiving LPI

0: PCS is not currently receiving LPI

Rx LPI indication

1: Rx PCS is currently receiving LPI

0: PCS is not currently receiving LPI

7:3

Reserved

PCS receive link status RO

1: PCS receive link up

0: PCS receive link down

1:0

Reserved

Table 92 •

EEE Capability, Address 3.20

Bit

Name

Access Description

15:3 Reserved

Reserved

1000BASE-T EEE RO

1: EEE is supported for 1000BASE-T

0: EEE is not supported for 1000BASE-T

100BASE-TX

EEE

1: EEE is supported for 100BASE-TX

0: EEE is not supported for 100BASE-TX

Reserved

Table 93 •

EEE Wake Error Counter, Address 3.22

Bit

Name

Access Description

15:0 Wake error counter RO

Count of wake time faults for a PHY

Table 94 •

EEE Advertisement, Address 7.60

Bit

Name

Access Description

Default

15:3 Reserved

Reserved

1000BASE-T EEE R/W

1: Advertise that the 1000BASE-T has EEE

capability

0: Do not advertise that the 1000BASE-T has EEE

capability

Table 91 •

PCS Status 1, Address 3.1 (continued)

Bit

Name

Access Description

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