VSC8504-02 datasheet(89/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

4.6.3

GPIO Control 2

The GPIO control 2 register configures the functionality of the COMA_MODE input pins, and provides

control for possible GPIO pin options.

Table 76 •

GPIO Control 2, Address 14G (0x0E)

Bit

Name

Access Description

Default

15:14

GPIO12 and GPIO13

R/W

GPIO12 and GPIO13 control.

00: Reserved

01: Reserved.

10: Reserved.

11: GPIO12/GPIO13 operation. Controlled

by MII registers 15G to 17G.

COMA_MODE output

enable (active low)

R/W

1: COMA_MODE pin is an input.

0: COMA_MODE pin is an output.

COMA_MODE output

data

R/W

Value to output on the COMA_MODE pin

when it is configured as an output.

COMA_MODE input data RO

Data read from the COMA_MODE pin.

Tri-state enable for

two-wire serial bus

R/W

1: Tri-states two-wire serial bus output

signals instead of driving them high. This

allows those signals to be pulled above

VDD25 using an external pull-up resistor.

0: Drive two-wire serial bus output signals

to high and low values as appropriate.

Tri-state enable for LEDs R/W

1: Tri-state LED output signals instead of

driving them high. This allows the signals

to be pulled above VDDIO using an external

pull-up resistor.

0: Drive LED bus output signals to high and

low values.

Reserved

7:6

GPIO11

R/W

GPIO11 control.

00: Reserved

01: Reserved

10: Reserved

11: Controlled by MII registers 15G to 17G

5:4

GPIO10

R/W

GPIO10 control.

00: Reserved

01: Reserved

10: Reserved

11: Controlled by MII registers 15G to 17G

3:2

GPIO9/FASTLINK_FAIL

R/W

GPIO9/FASTLINK_FAIL control.

00: FASTLINK_FAIL operation

01: Reserved

10: Reserved

11: Controlled by MII registers 15G to 17G

1:0

GPIO8/I2C_SDA

R/W

GPIO8/I2C_SDA control.

00: I2C_SDA operation

01: Reserved

10: Reserved

11: Controlled by MII registers 15G to 17G

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