VSC8504-02 datasheet(84/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

4.5.5

MAC SerDes Status

The register at address 20E3 consists of the bits that provide access to MAC SerDes status. The

following table shows the settings available.

4.5.6

Media SerDes Transmit Good Packet Counter

The register at address 21E3 consists of the bits that provide status of the media SerDes transmit good

packet counter. The following table shows the settings available.

4.5.7

Media SerDes Transmit CRC Error Counter

The register at address 22E3 consists of the bits that provide status of the media SerDes transmit packet

count that had a CRC error. The following table shows the settings available.

4.5.8

Media SerDes PCS Control

The register at address 23E3 consists of the bits that provide access to and control over Media SerDes

PCS control. The following table shows the settings available.

Table 64 •

MAC SerDes Status, Address 20E3 (0x14)

Bit

Name

Access Description

Reserved

MAC comma detect

Super-sticky bit. Cleared upon SW reset.

1: Comma detected

0: Comma not detected

QSGMII sync status

12:0 Reserved

Reserved

Table 65 •

Media SerDes Tx Good Packet Counter, Address 21E3 (0x15)

Bit

Name

Access Description

Tx good packet counter active

1: Transmit good packet counter active

Reserved

13:0 Tx good packet count

Transmit good packet count modulo 10000

Table 66 •

Media SerDes Tx CRC Error Counter, Address 22E3 (0x16)

Bit

Name

Access Description

15:8 Reserved

Reserved

7:0

Tx CRC packet count RO

Transmit CRC packet count (saturates at 255)

Table 67 •

Media SerDes PCS Control, Address 23E3 (0x17)

Bit

Name

Access Description

Default

15:14 Reserved

Reserved

Media interface autonegotiation

parallel-detection

R/W

Sticky bit.

1: SerDes media autonegotiation

parallel detect enabled

Reserved

Force advertised ability

R/W

1: Force 16-bit advertised ability

from register 25E3.15:0

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