VSC8504-02 datasheet(82/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

4.5.1

MAC SerDes PCS Control

The register at address 16E3 consists of the bits that provide access to and control over MAC SerDes

PCS block. The following table shows the settings available.

29E3

Fiber Media CRC Error Counter

30E3

Reserved

Table 60 •

MAC SerDes PCS Control, Address 16E3 (0x10)

Bit

Name

Access Description

Default

MAC interface disable

R/W

Sticky bit.

1: 1000BASE-X MAC interface disable when

media link down.

MAC interface restart

R/W

Sticky bit.

1: 1000BASE-X MAC interface restart on

media link change.

MAC interface PD enable R/W

Sticky bit.

1: MAC interface autonegotiation parallel

detect enable.

MAC interface

autonegotiation restart

R/W

Self-clearing bit.

1: Restart MAC interface autonegotiation.

Force advertised ability

R/W

1: Force 16-bit advertised ability from register

18E3.

10:8 SGMII preamble control

R/W

000: No effect on the start of packet.

001: If both the first two nibbles of the 10/100

packet are not 0x5, a byte of 0x55 must be

prefixed to the output, otherwise there will be

no effect on the start of packet.

010: If both the first two nibbles of the 10/100

packet are not 0x5, a byte of 0x55 must be

prefixed to the output. An additional byte of

0x55 must be prefixed to the output if the

next two nibbles are also not 0x5.

011–111: Reserved.

001

7MAC SerDes

autonegotiation enable

R/W

Sticky bit.

1: MAC SerDes ANEG enable.

SerDes polarity at input of

MAC

R/W

1: Invert polarity of signal received at input of

MAC.

SerDes polarity at output

of MAC

R/W

1: Invert polarity of signal at output of MAC.

Fast link status enable

R/W

1: Use fast link fail indication as link status

indication to MAC SerDes.

0: Use normal link status indication to MAC

SerDes.

Reserved

R/W

Reserved.

2:0

Reserved

Reserved.

Table 59 •

Extended Registers Page 3 Space (continued)

Address Name

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