VSC8504-02 datasheet(66/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

The following information applies to the extended control and status bits:

•

When bit 22.15 is set, the link integrity state machine is bypassed and the PHY is forced into a link

pass status.

•

When bits 22.11:10 are set to 00, the squelch threshold levels are based on the IEEE standard for

10BASE-T. When set to 01, the squelch level is decreased, which can improve the bit error rate

performance on long loops. When set to 10, the squelch level is increased and can improve the bit

error rate in high-noise environments.

•

When bit 22.9 is set, all sticky register bits retain their values during a software reset. Clearing this

bit causes all sticky register bits to change to their default values upon software reset. Super-sticky

bits retain their values upon software reset regardless of the setting of bit 22.9.

•

When bit 22.0 is set, if a write to any PHY register (registers 0–31, including extended registers), the

same write is broadcast to all PHYs. For example, if bit 22.0 is set to 1 and a write to PHY0 is

executed (register 0 is set to 0x1040), all PHYs' register 0s are set to 0x1040. Table 18,

page 45Disabling this bit restores normal PHY write operation. Reads are still possible when this bit

is set, but the value that is read corresponds only to the particular PHY being addressed.

4.2.21

Extended PHY Control Set 1

The following table shows the settings available.

11:10

10BASE-T squelch control

R/W

Sticky bit.

00: Normal squelch

01: Low squelch

10: High squelch

11: Reserved

Sticky reset enable

R/W

Super-sticky bit.

1: Enabled

EOF Error

This bit is self-clearing.

1: EOF error detected

10BASE-T disconnect state RO

This bit is self-clearing.

1: 10BASE-T link disconnect detected

10BASE-T link status

1: 10BASE-T link active

5:1

Reserved

SMI broadcast write

R/W

Sticky bit.

1: Enabled

Table 39 •

Extended PHY Control 1, Address 23 (0x17)

Bit

Name

Access Description

Default

15:13 Reserved

R/W

Reserved

MAC interface mode R/W

Super-sticky bit.

0: SGMII

1: 1000BASE-X.

Note: Register 19G.15:14 must be = 00

for this selection to be valid.

AMS preference

R/W

Super-sticky bit.

1: Cat5 copper preferred.

0: SerDes fiber/SFP preferred.

Table 38 •

Extended Control and Status, Address 22 (0x16) (continued)

Bit

Name

Access Description

Default

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