VSC8504-02 datasheet(33/131 Pages) MICROSEMI

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Functional Descriptions

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

3.10.1

Low Power State

In the low power state, all major digital blocks are powered down. However, the SMI interface (MDC,

MDIO, and MDINT) functionality is provided.

In this state, the PHY monitors the media interface pins for signal energy. The PHY comes out of low

power state and transitions to the normal operating state when signal energy is detected on the media.

This happens when the PHY is connected to one of the following:

•

Autonegotiation-capable link partner

•

Another PHY in enhanced ActiPHY LP wake-up state

In the absence of signal energy on the media pins, the PHY periodically transitions from low-power state

to LP wake-up state, based on the programmable sleep timer (register bits 20E1.14:13). The actual sleep

time duration is randomized from –80 ms to 60 ms to avoid two linked PHYs in ActiPHY mode entering a

lock-up state during operation.

3.10.2

Link Partner Wake-Up State

In the link partner wake-up state, the PHY attempts to wake up the link partner. Up to three complete FLP

bursts are sent on alternating pairs A and B of the Cat5 media for a duration based on the wake-up timer,

which is set using register bits 20E1.12:11.

In this state, SMI interface (MDC, MDIO, and MDINT) functionality is provided.

After sending signal energy on the relevant media, the PHY returns to the low power state.

3.10.3

Normal Operating State

In the normal operating state, the PHY establishes a link with a link partner. When the media is

unplugged or the link partner is powered down, the PHY waits for the duration of the programmable link

status time-out timer, which is set using register bit 28.7 and bit 28.2. It then enters the low power state.

3.11

Media Recovered Clock Outputs

For Synchronous Ethernet applications, the VSC8504-02 includes two recovered clock output pins,

RCVRDCLK1 and RCVRDCLK2, controlled by registers 23G and 24G, respectively. The recovered clock

pins are synchronized to the clock of the active media link.

To enable recovered clock output, set register 23G or 24G, bit 15, to 1. By default, the recovered clock

output pins are disabled and held low, including when NRESET is asserted. Registers 23G and 24G also

control the PHY port for clock output, the clock source, the clock frequency (either 25 MHz, 31.25 MHz,

or 125 MHz), and squelch conditions.

Note: When EEE is enabled on a link, the use of the recovered clock output is not recommended due to long

holdovers occurring during EEE Quiet/Refresh cycles.

3.11.1

Clock Selection Settings

On each pin, the recovered clock supports the following sources, as set by registers 23G or 24G, bits 2:0:

•

Fiber SerDes media recovered clock

•

Copper PHY recovered clock

•

Copper PHY media transmitter TCLK output (RCVRDCLK1 only.) For more information, see

Table 64, page 73 and Table 65, page 73.

Note: When using the automatic media sense feature, the recovered clock output cannot automatically change

between each active media. Changing the media source must be managed through the recovered clock

Adjust the squelch level to enable 1000BASE-T master mode recovered clock for SyncE operation. This

is accomplished by changing the 23G and 24G register bits 5:4 to 01. This setting also provides clock out

for 10BASE-T operation. For 1000BASE-T master mode, the clock is based on the VSC8504-02

REFCLK input, which is a local clock.

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