VSC8504-02 datasheet(67/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

Note: After configuring bits 13:8 of the extended PHY control register set 1, a software reset (register 0, bit 15)

must be written to change the device operating mode. On read, these bits only indicate the actual

operating mode and not the pending operating mode setting before a software reset has taken place.

4.2.22

Extended PHY Control Set 2

The second set of extended controls is located in register 24 in the main register space for the device.

The following table shows the settings and readouts available.

10:8

Media operating

mode

R/W

Super-sticky bits.

000: Cat5 copper only.

001: SerDes fiber/SFP protocol transfer mode

only.

010: 1000BASE-X fiber/SFP media only with

autonegotiation performed by the PHY.

011: 100BASE-FX fiber/SFP on the fiber media

pins only.

101: Automatic media sense (AMS) with Cat5

media or SerDes fiber/SFP protocol transfer

mode.

110: AMS with Cat5 media or 1000BASE-X

fiber/SFP media with autonegotiation performed

by PHY.

111: AMS with Cat5 media or 100BASE-FX

fiber/SFP media.

100: AMS.

000

7:6

Force AMS override R/W

Sticky bits.

00: Normal AMS selection

01: Force AMS to select SerDes media only

10: Force AMS to select copper media only

11: Reserved

5:4

Reserved

Reserved.

Far-end loopback

mode

R/W

1: Enabled.

2:0

Reserved

Reserved.

Table 40 •

Extended PHY Control 2, Address 24 (0x18)

Bit

Name

Access Description

Default

15:13 100BASE-TX edge

rate control

R/W

Sticky bit.

011: +5 edge rate (slowest)

010: +4 edge rate

001: +3 edge rate

000: +2 edge rate

111: +1 edge rate

110: Default edge rate

101: –1 edge rate

100: –2 edge rate (fastest)

001

PICMG 2.16 reduced

power mode

R/W

Sticky bit.

1: Enabled

11:6

Reserved

Table 39 •

Extended PHY Control 1, Address 23 (0x17) (continued)

Bit

Name

Access Description

Default

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