VSC8504-02 datasheet(68/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

Note: When bits 5:4 are set to jumbo packet mode, the default maximum packet values are based on 100 ppm

driven reference clock to the device. Controlling the ppm offset between the MAC and the PHY as

specified in the bit description results in a higher jumbo packet length.

4.2.23

Interrupt Mask

These bits control the device interrupt mask. The following table shows the settings available.

Note: When bit 25.15 is set, the MDINT pin is enabled. When enabled, the state of this pin reflects the state of

bit 26.15. Clearing this bit only inhibits the MDINT pin from being asserted. Also, before enabling this bit,

read register 26 to clear any previously inactive interrupts pending that will cause bit 25.15 to be set.

5:4

Jumbo packet mode

R/W

Sticky bit.

00: Normal IEEE 1.5 kB packet length

01: 9 kB jumbo packet length (12 kB with

60 ppm or better reference clock)

10: 12 kB jumbo packet length (16 kB with

70 ppm or better reference clock)

11: Reserved

3:1

Reserved

1000BASE-T

connector loopback

R/W

1: Enabled

Table 41 •

Interrupt Mask, Address 25 (0x19)

Bit

Name

Access Description

Default

MDINT interrupt status enable

R/W

Sticky bit. 1: Enabled.

Speed state change mask

R/W

Sticky bit. 1: Enabled.

Link state change mask

R/W

Sticky bit. 1: Enabled.

FDX state change mask

R/W

Sticky bit. 1: Enabled.

Autonegotiation error mask

R/W

Sticky bit. 1: Enabled.

Autonegotiation complete mask

R/W

Sticky bit. 1: Enabled.

Inline powered device (PoE) detect mask R/W

Sticky bit. 1: Enabled.

Symbol error interrupt mask

R/W

Sticky bit. 1: Enabled.

Fast link failure interrupt mask(1)

The interrupt is only valid for 100 Mbps and 1000 Mbps speeds. Notification at 10 Mbps speed requires

use of the FASTLINK-FAIL pin.

R/W

Sticky bit. 1: Enabled.

6:5

Reserved

R/W

AMS media changed mask(2)

If hardware interrupts are not used, the mask can still be set and the status polled for changes.

R/W

Sticky bit. 1: Enabled.

False carrier interrupt mask

R/W

Sticky bit. 1: Enabled.

Link speed downshift detect mask

R/W

Sticky bit. 1: Enabled.

Master/Slave resolution error mask

R/W

Sticky bit. 1: Enabled.

RX_ER interrupt mask

R/W

Sticky bit. 1: Enabled.

Table 40 •

Extended PHY Control 2, Address 24 (0x18) (continued)

Bit

Name

Access Description

Default

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