VSC8504-02 datasheet(99/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

4.7.5

EEE Link Partner Advertisement

All the bits in the EEE LP Advertisement register are read only. A write to the EEE LP advertisement

the link partner's EEE advertisement register. The following table shows the bit assignments for the EEE

advertisement register.

The following table shows the bit assignments for the 802.3bf registers. When the link is down, 0 is the

value returned. cl45reg1_1801 would be device address of 1 and register address of 1801.

100BASE-TX

EEE

R/W

1: Advertise that the 100BASE-TX has EEE

capability

0: Do not advertise that the 100BASE-TX has EEE

capability

Reserved

Table 95 •

EEE Advertisement, Address 7.61

Bit

Name

Access Description

15:3 Reserved

Reserved

1000BASE-T EEE RO

1: Link partner is advertising EEE capability for 1000BASE-T

0: Link partner is not advertising EEE capability for

1000BASE-T

100BASE-TX

EEE

1: Link partner is advertising EEE capability for 100BASE-TX

0: Link partner is not advertising EEE capability for

100BASE-TX

Reserved

Table 96 •

802.3bf Registers

Name

Function

1.1801

cl45reg1_1801_val[15:0]

Tx maximum delay through PHY (PMA/PMD/PCS)

1.1803

cl45reg1_1803_val[15:0]

Tx minimum delay through PHY (PMA/PMD/PCS)

1.1805

cl45reg1_1805_val[15:0]

Rx maximum delay through PHY (PMA/PMD/PCS)

1.1807

cl45reg1_1807_val[15:0]

Rx minimum delay through PHY (PMA/PMD/PCS)

4.1801

cl45reg4_1801_val[15:0]

Tx maximum delay through xMII (SGMII, QSGMII,

including FIFO variations)

4.1803

cl45reg4_1803_val[15:0]

Tx minimum delay through xMII (SGMII, QSGMII,

including FIFO variations)

4.1805

cl45reg4_1805_val[15:0]

Rx maximum delay through xMII (SGMII, QSGMII,

including FIFO variations)

4.1807

cl45reg4_1807_val[15:0]

Rx minimum delay through xMII (SGMII, QSGMII,

including FIFO variations)

Table 94 •

EEE Advertisement, Address 7.60 (continued)

Bit

Name

Access Description

Default

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