VSC8504-02 datasheet(62/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

4.2.11

MMD Access Control Register

The bits in register 13 of the main register space are a window to the EEE registers as defined in

IEEE 802.3az-2010 Clause 45.

4.2.12

MMD Address or Data Register

The bits in register 14 of the main register space are a window to the EEE registers as defined in

IEEE 802.3az-2010 Clause 45.

4.2.13

1000BASE-T Status Extension 1

communications. The following table shows the readouts available.

4.2.14

100BASE-TX/FX Status Extension

the status of the device's 100BASE-TX/100BASE-FX operation.

Table 29 •

MMD EEE Access, Address 13 (0x0D)

Bit

Name

Access Description

15:14 Function

R/W

00: Address

01: Data, no post increment

10: Data, post increment for read and write

11: Data, post increment for write only

13:5

Reserved R/W

Reserved

4:0

DVAD

R/W

Device address as defined in IEEE 802.3az-2010 table

45–1

Table 30 •

MMD Address or Data Register, Address 14 (0x0E)

Bit

Name

Access Description

15:0 Register Address/Data R/W

When register 13.15:14 = 2'b00, address of register of

the device that is specified by 13.4:0. Otherwise, the

data to be written to or read from the register.

Table 31 •

1000BASE-T Status Extension 1, Address 15 (0x0F)

Bit

Name

Access Description

Default

1000BASE-X FDX capability RO

1: PHY is 1000BASE-X FDX capable 1

1000BASE-X HDX capability RO

1: PHY is 1000BASE-X HDX capable 1

1000BASE-T FDX capability RO

1: PHY is 1000BASE-T FDX capable 1

1000BASE-T HDX capability RO

1: PHY is 1000BASE-T HDX capable 1

11:0

Reserved

0x000

Table 32 •

100BASE-TX/FX Status Extension, Address 16 (0x10)

Bit Name

Access Description

Default

100BASE-TX/FX Descrambler

1: Descrambler locked

100BASE-TX/FX lock error

Self-clearing bit.

1: Lock error detected

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