VSC8504-02 datasheet(60/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

4.2.7

Transmit Autonegotiation Next Page

The settings in register 7 in the main registers space provide information about the number of pages in

an autonegotiation sequence. The following table shows the settings available.

4.2.8

Autonegotiation Link Partner Next Page Receive

The bits in register 8 of the main register space work together with register 7 to determine certain aspects

of the LP autonegotiation. The following table shows the possible readouts.

4.2.9

1000BASE-T Control

The VSC8504-02's 1000BASE-T functionality is controlled by the bits in register 9 of the main register

space. The following table shows the settings and readouts available.

Table 25 •

Autonegotiation Next Page Transmit, Address 7 (0x07)

Bit

Name

Access Description

Default

R/W

1: More pages follow

Reserved

Message page

R/W

1: Message page

0: Unformatted page

Acknowledge 2

R/W

1: Complies with request

0: Cannot comply with request

Toggle

1: Previous transmitted LCW = 0 0:

Previous transmitted LCW = 1

10:0 Message/unformatted code R/W

00000000001

Table 26 •

Autonegotiation LP Next Page Receive, Address 8 (0x08)

Bit

Name

Access Description

Default

LP next page

1: More pages follow

Acknowledge

1: LP acknowledge

LP message page

1: Message page

0: Unformatted page

LP acknowledge 2

1: LP complies with request

LP toggle

1: Previous transmitted LCW = 0

0: Previous transmitted LCW = 1

10:0 LP message/unformatted code RO

All zeros

Table 27 •

1000BASE-T Control, Address 9 (0x09)

Bit

Name

Access Description

Default

15:13 Transmitter test mode R/W

000: Normal

001: Mode 1: Transmit waveform test

010: Mode 2: Transmit jitter test as master

011: Mode 3: Transmit jitter test as slave

100: Mode 4: Transmitter distortion test

101–111: Reserved

000

Master/slave manual

configuration

R/W

1: Master/slave manual configuration enabled 0

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