VSC8504-02 datasheet(22/131 Pages) MICROSEMI

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Functional Descriptions

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

3.1.7.2

Media interface 10/100/1000BASE-T Cu-SFP

Use the following settings to configure the fiber/SFP media interface for protocol transfer mode.

•

Set register 23 bits 10:8 = 001.

•

Set register 0 bit 12 = 1 (enable autonegotiation).

For QSGMII only port 0 is used.

Note: Whenever there is a mode change a software reset (register 0 bit 15) is required to make the mode

change effective. This register is cleared when read.

3.1.8

1000BASE-X MAC-to-Cat5 Link Partner

The following illustration and sections show the register settings used to configure a 1000BASE-X MAC-

to-Cat5 Link Partner.

Figure 13 •

1000BASE-X MAC-to-Cat5 Link Partner

In this mode the device provides data throughput of 1000 Mbps only.

3.1.8.1

MAC interface

Use the following settings to configure the MAC interface.

•

Set register 19G bits 15:14 = 00.

•

Set register 23 (main register) bit 12 = 1.

3.1.8.2

Clause 37 MAC Autonegotiation

For clause 37 MAC autonegotiation, set register 16E3 bit 7 = 1.

Note: Whenever there is a mode change a software reset (register 0 bit 15) is required to make the mode

change effective. This register is cleared when read.

3.2

SerDes MAC Interface

The VSC8504-02 SerDes MAC interface performs data serialization and deserialization functions using

an integrated SerDes block. The interface operates in 1000BASE-X compliant mode, QSGMII mode, or

SGMII mode. The SerDes and enhanced SerDes blocks have the termination resistor integrated into the

device. The SerDes block also has the AC decoupling capacitors integrated in the receive path.

Integrated AC decoupling is not supported in the enhanced SerDes block (QSGMII SerDes). Register

19G is a global register and only needs to be set once to configure the device. The other register bits are

configured on a per-port basis and the operation either needs to be repeated for each port, or a

broadcast write needs to be used by setting register 22, bit 0 to configure all the ports simultaneously.

QSGMII/SGMII,

1000BASE-X,

PMA, PCS, and

AutoNeg

MDI Twisted Pair,

PMA, PCS, and

AutoNeg

1000BASE-T LP

Port 0

1000BASE-X

MAC

1000BASE-T

SFP Module

100BASE-FX,

PMA, PCS, and

AutoNeg

1000BASE-X Fiber,

10/100/1000BASE-T

Copper SFP, PMA,

PCS, and AutoNeg

FIBROP/N_0

TDP_0

TDN_0

RDP_0

RDN_0

FIBRIP/N_0

TXVP_0

TXVN_0

TXVP_3

TXVN_3

SIGDET0

•

TDP_3

TDN_3

RDP_3

RDN_3

FIBROP/N_3

FIBRIP/N_3

SIGDET3

Port 3

Fiber

1000BASE-X

MAC

1000BASE-T

SFP Module

Fiber

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