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VSC8504-02 датащи(PDF) 29 Page - Microsemi Corporation

номер детали VSC8504-02
подробное описание детали  Quad-Port 10/100/1000BASE-T PHY with Synchronous Ethernet and QSGMII/SGMII MAC
PDF  131 Pages
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производитель  MICROSEMI [Microsemi Corporation]
домашняя страница  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

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Functional Descriptions
VMDS-10507 VSC8504-02 Datasheet Revision 4.2
18
media link established. The following table shows the possible link conditions based on preference
settings.
The status of the media mode selected by the AMS can be read from device register 20E1, bits 7:6. It
indicates whether copper media, SerDes media, or no media is selected. Each PHY has four automatic
media sense modes. The difference between the modes is based on the SerDes media modes:
SGMII or QSGMII MAC to AMS and 1000BASE-X SerDes
SGMII or QSGMII MAC to AMS and 100BASE-FX SerDes
SGMII or QSGMII MAC to AMS and SGMII (protocol transfer)
For more information about SerDes media mode functionality with AMS enabled, see SerDes Media
Interface, page 13.
3.7
Reference Clock
The device reference clock supports both 25 MHz and 125 MHz clock signals. The reference clock can
be either differential or single-ended. If differential, it must be capacitively coupled and LVDS compatible.
3.7.1
Configuring the Reference Clock
The REFCLK_SEL2 pin configures the reference clock speed. The following table shows the functionality
and associated reference clock frequency.
3.7.2
Single-Ended REFCLK Input
To use a single-ended reference clock, an external resistor network is required. The purpose of the
network is to limit the amplitude and to adjust the center of the swing. The configurations for a single-
ended REFCLK, with the clock centered at 1 V and a 500 mV peak-to-peak swing, are shown in the
following illustrations.
Figure 20 •
2.5 V CMOS Single-Ended REFCLK Input Resistor Network
Table 4 •
AMS Media Preferences
Preference
Setting
Cat5 Linked,
Fiber Not Linked
SerDes Linked,
Cat5 Not Linked
Cat5 Linked,
SerDes Attempts
to Link
SerDes Linked,
Cat5 Attempts
to Link
Both Cat5 and
SerDes Attempt
to Link
SerDes
Cat5
SerDes
SerDes
SerDes
SerDes
Cat5
Cat5
SerDes
Cat5
Cat5
Cat5
Table 5 •
REFCLK Frequency Selection
REFCLK_SEL2 Frequency
025 MHz
1125 MHz
V
DD1A
V
SSA
V
DD1A
REFCLK_P
REFCLK_N
220
Ω
910
Ω
2.5 V
CMOS



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