VSC8504-02 datasheet(77/131 Pages) MICROSEMI

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Registers

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

The following information applies to the EPG control number 1:

•

Do not run the EPG when the VSC8504-02 is connected to a live network.

•

bit 29E1.13 (continuous EPG mode control): When enabled, this mode causes the device to send

continuous packets. When disabled, the device continues to send packets only until it reaches the

next 10,000-packet increment mark. It then ceases to send packets.

•

The 6-byte destination address in bits 9:6 is assigned one of 16 addresses in the range of 0xFF FF

FF FF FF F0 through 0xFF FF FF FF FF FF.

•

The 6-byte source address in bits 5:2 is assigned one of 16 addresses in the range of 0xFF FF FF

FF FF F0 through 0xFF FF FF FF FF FF.

•

If any of bits 13:0 are changed while the EPG is running (bit 14 is set to 1), bit 14 must be cleared

and then set back to 1 for the change to take effect and to restart the EPG.

4.3.7

Ethernet Packet Generator Control 2

aspects of the EPG testing feature. The following table shows the settings available.

Note: If any of bits 15:0 in this register are changed while the EPG is running (bit 14 of register 29E1 is set to

1), that bit (29E1.14) must first be cleared and then set back to 1 for the change to take effect and to

restart the EPG.

4.4

Extended Page 2 Registers

To access the extended page 2 registers (16E2–30E2), enable extended register access by writing

0x0002 to register 31. For more information, see Table 46, page 61.

When extended page 2 register access is enabled, reads and writes to registers 16–30 affect the

extended registers 16E2–30E2 instead of those same registers in the IEEE-specified register space.

Registers 0–15 are not affected by the state of the extended page register access.

Writing 0x0000 to register 31 restores the main register access.

The following table lists the addresses and register names in the extended register page 2 space. These

registers are accessible only when the device register 31 is set to 0x0002.

Payload type

R/W

1: Randomly generated payload pattern

0: Fixed based on payload pattern

Bad frame check

sequence (FCS)

generation

R/W

1: Generate packets with bad FCS

0: Generate packets with good FCS

Table 54 •

EPG Control Register 2, Address 30E1 (0x1E)

Bit

Name

Access Description

Default

15:0 EPG packet payload R/W

Data pattern repeated in the payload of

packets generated by the EPG

0x00

Table 55 •

Extended Registers Page 2 Space

Address

Name

16E2

Cu PMD Transmit Control

17E2

EEE Control

18E2-29E2

Reserved

30E2

Ring Resiliency Control

Table 53 •

EPG Control Register 1, Address 29E1 (0x1D) (continued)

Bit

Name

Access Description

Default

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