VSC8504-02 datasheet(49/131 Pages) MICROSEMI

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Functional Descriptions

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

Figure 36 •

Test Access Port and Boundary Scan Architecture

After a TAP reset, the device identification register is serially connected between TDI and TDO by

default. The TAP instruction register is loaded either from a shift register when a new instruction is shifted

in, or, if there is no new instruction in the shift register, a default value of 6'b100000 (IDCODE) is loaded.

Using this method, there is always a valid code in the instruction register, and the problem of toggling

instruction bits during a shift is avoided. Unused codes are mapped to the BYPASS instruction.

3.17.9

JTAG Instruction Codes

The VSC8504-02 supports the following instruction codes:

Table 12 •

JTAG Instruction Codes

Instruction Code

Description

BYPASS

The bypass register contains a single shift-register stage and is

used to provide a minimum-length serial path (one TCK clock

period) between TDI and TDO to bypass the device when no test

operation is required.

CLAMP

Allows the state of the signals driven from the component pins to

be determined from the boundary scan register while the bypass

While the CLAMP instruction is selected, the signals driven from

the component pins do not change.

EXTEST

Allows tests of the off-chip circuitry and board-level

interconnections by sampling input pins and loading data onto

output pins. Outputs are driven by the contents of the boundary

scan cells, which have to be updated with valid values, with the

PRELOAD instruction, prior to the EXTEST instruction.

Boundary Scan

Test Access Port

Controller

Control

Select

TDO Enable

TDI

TMS

NTRST

TCK

Control

MUX,

DFF

TDO

Instruction Register,

Instruction Decode

Control

Bypass Register

Device Identification

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