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VSC8504-02 датащи(PDF) 103 Page - Microsemi Corporation

номер детали VSC8504-02
подробное описание детали  Quad-Port 10/100/1000BASE-T PHY with Synchronous Ethernet and QSGMII/SGMII MAC
PDF  131 Pages
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производитель  MICROSEMI [Microsemi Corporation]
домашняя страница  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC8504-02 датащи(HTML) 103 Page - Microsemi Corporation

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Electrical Specifications
VMDS-10507 VSC8504-02 Datasheet Revision 4.2
92
Figure 41 •
SGMII DC Input Definitions
5.1.6
Enhanced SerDes Interface (QSGMII)
All DC specifications for the enhanced SerDes interface are compliant with QSGMII Specification
Revision 1.3 and meet or exceed the requirements in the standard. They are also compliant with OIF-
CEI-02.0 requirements where applicable.
The enhanced SerDes interface supports the following operating modes: SGMII, QSGMII, and SFP. The
values in the following table apply to the modes specified in the condition column.
The following table shows the DC specifications for the enhanced SerDes driver.
Input differential peak-to-peak
voltage
|VID|
100
1000
mV
Input common-mode voltage(1)
VICM
0VDD_A(2)
mV
Without any
differential signal
Receiver differential input
impedance
RI
80
120
Ω
Input differential hysteresis,
SGMII mode
VHYST
25
mV
1.
SGMII compliancy requires external AC-coupling. When interfacing with specific Microsemi devices, DC-
coupling is possible. For more information, contact your local Microsemi sales representative.
2.
The common-mode voltage is only limited by the maximum and minimum input voltage range and the
input signal’s differential amplitude.
Table 103 •
Enhanced SerDes Driver DC Specifications
Parameter
Symbol Minimum
Maximum
Unit Condition
Output differential peak voltage,
SFP and QSGMII modes
|VODp|
250
400
mV
VDD_VS =1.0 V
RL =100 Ω ±1%
maximum drive
Output differential peak voltage,
SGMII mode(1)
|VODp|
150
400
mV
VDD_VS =1.0 V
RL =100 Ω ±1%
DC output impedance,
single-ended, SGMII mode
RO
40
140
Ω
VC =1.0 V
See Figure 40,
page 91
RO mismatch between A and B,
SGMII mode(2)
ΔRO
10
%
VC =1.0 V
See Figure 40,
page 91
Change in |VOD| between 0 and 1,
SGMII mode
Δ|VOD|25
mV
RL =100 Ω ±1%
Change in VOS between 0 and 1,
SGMII mode
ΔVOS
25
mV
RL =100 Ω ±1%
Table 102 •
SerDes Receiver DC Specifications (continued)
Parameter
Symbol Minimum
Maximum
Unit Condition
VID = VIA –VIB
VIC = ½ (VIA + VIB)
VIB
VIA



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