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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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VSC8504-02 датащи(PDF) 107 Page - Microsemi Corporation |
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VSC8504-02 датащи(HTML) 107 Page - Microsemi Corporation |
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107 / 131 page  Electrical Specifications VMDS-10507 VSC8504-02 Datasheet Revision 4.2 96 5.2.3 SerDes Outputs The values listed in the following table are valid for all configurations, unless otherwise noted. Recovered clock cycle time tRCYC 32.0 ns Recovered clock cycle time tRCYC 40.0 ns Frequency stability ƒSTABILITY 50 ppm Duty cycle, master mode DC 40 50 60 % Clock rise time and fall time tR, tF 600 ps 20% to 80% Peak-to-peak jitter, copper media interface (1000BASE- T slave mode) JPPCLK_Cu 400 ps 10K samples Peak-to-peak jitter, fiber media interface, 100BASE-FX JPPCLK_FiFX 1.2 ns 10K samples Peak-to-peak jitter, fiber media interface, 1000BASE-X JPPCLK_FiX 250 ps 10K samples Table 109 • SerDes Outputs AC Specifications Parameter Symbol Minimum Maximum Unit Condition VOD ringing compared to VS, SGMII mode VRING ±10 % RL = 100 Ω ±1% VOD rise time and fall time, SGMII mode tR, tF 100 200 ps 20% to 80% of VS RL = 100 Ω ±1% Differential peak-to-peak output voltage VOD 30 mV Tx disabled Differential output return loss, 50 MHz to 625 MHz RLO_DIFF ≥10 dB RL = 100 Ω ±1% Differential output return loss, 625 MHz to 1250 MHz RLO_DIFF 10–10 × log (ƒ/625 MHz) dB RL = 100 Ω ±1% Common-mode return loss, 50 MHz to 625 MHz RLOCM 6dB Interpair skew, SGMII mode tSKEW 20 ps Table 108 • Recovered Clock AC Characteristics (continued) Parameter Symbol Minimum Typical Maximum Unit Condition |
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