VSC8504-02 datasheet(106/131 Pages) MICROSEMI

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Electrical Specifications

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

5.2.2

Recovered Clock

This section provides the AC characteristics for the recovered clock output signals. The following

illustration shows the test circuit for the recovered clock output signals.

Figure 42 •

Test Circuit for Recovered Clock Output Signals

The following table shows the AC specifications for the RCVRDCLK1 and RCVRDCLK2 outputs.

RefClk input RMS jitter

requirement, bandwidth

between 500 kHz and

15 MHz(1)

To meet jitter

generation of 1G

output data per

IEEE 802.3z

RefClk input RMS jitter

requirement, bandwidth

between 15 MHz and

40 MHz(1)

To meet jitter

generation of 1G

output data per

IEEE 802.3z

RefClk input RMS jitter

requirement, bandwidth

between 40 MHz and

80 MHz(1)

100

To meet jitter

generation of 1G

output data per

IEEE 802.3z

Jitter gain from RefClk

to SerDes output,

bandwidth between

0 MHz and 0.1 MHz

0.3

Jitter gain from RefClk

to SerDes output,

bandwidth between

0.1 MHz and 7 MHz

Jitter gain from RefClk

to SerDes output,

bandwidth above 7 MHz

1–20 × log

(ƒ/7 MHz)

3–20 × log

(ƒ/7 MHz)

Maximum RMS jitter allowed at the RefClk input for the given bandwidth.

Table 108 •

Recovered Clock AC Characteristics

Parameter

Symbol

Minimum

Typical Maximum

Unit Condition

Recovered clock

frequency

ƒ125.00

MHz

Recovered clock

frequency

31.25

MHz

Recovered clock

frequency

25.00

MHz

Recovered clock cycle

time

tRCYC

8.0

Table 107 •

Reference Clock AC Characteristics for QSGMII 125 MHz Differential Clock (continued)

Parameter

Symbol

Minimum

Typical Maximum

Unit Condition

Device Under Test

Signal Measurement Point

Ω

8 pF

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