CYT4DNJBJS datasheet(104/209 Pages) INFINEON

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Datasheet

104

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

SID50A

IDD1

VDDDcurrentininternalregulator

mode. Cortex®-M7/M0+ CPUs in

Sleep mode

–28

mA Clocks running at max

frequency, All CPUs in Sleep

mode.

VIDEOSS power switched off

All other peripherals,

peripheralclocks,interrupts,

CSV, DMA, ECO are disabled.

No IO toggling.

Typ: TA = 25°C, VDDD = 5.0 V,

process typ (TT)

Max: TA = 85°C, VDDD = 5.5 V,

process worst (FF)

SID50C

IDD1

VDDDcurrentininternalregulator

mode. Cortex®-M7/M0+ CPUs in

Sleep mode (room temp)

––

mA Clocks running at max

frequency, All CPUs in Sleep

mode.

VIDEOSS power switched off

All peripherals, peripheral

clocks, interrupts, CSV, DMA,

ECO are disabled. No IO

toggling.

Max: TA = 25°C, VDDD = 5.5 V,

process worst (FF)

SID50B

ICC1

VCCD current in external PMIC

mode

Cortex®-M7/M0+ CPUs in Sleep

mode

VIDEOSS in sleep mode (clocks

off)

–

500

mA Clocks running at max

frequency, All CPUs in Sleep

mode.

VIDEOSS in sleep mode

All other peripherals,

peripheralclocks,interrupts,

CSV, DMA, ECO are disabled.

No IO toggling.

Typ: TA = 25°C,

VCCD = 1.15 V,

process typ (TT)

Max: TA = 105°C,

VCCD = 1.21 V,

process worst (FF)

DeepSleep Mode

SID59

IDD_DS32A

VDDDcurrentininternalregulator

mode.

32 KB SRAM retention, LPECO

(4 MHz) operation in DeepSleep

mode.

–150

–

µA

Deep Sleep Mode (RTC and

EVTGEN operating, all other

peripherals off, CAN MRAM

disabled),

CM0+ and CM7_0 retain,

CM7_1 power switched OFF

Typ: TA = 25°C, VDDD = 5.0 V,

VCCD = 1.1 V, process typ (TT)

FPD-Link/MIPI Standby

currents not included

Table 26-3

DC specifications, CPU current, and transition time specifications (continued)

All specifications are valid for –40°C  TA  105°C and for 2.7 V to 5.5 V except where noted.

Spec ID

Parameter

Description

Min

Typ Max Units

Details/conditions

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